Active and continuous compensation of clock jitter in continuous time Delta-Sigma ADCs
Active and continuous compensation of clock jitter in continuous time Delta-Sigma ADCs
批准号:
444659113
负责人:
Professor Dr.-Ing. Dirk Killat
金额:
$0.0万
依托单位国家:
德国
项目类别:
Research Grants
财政年份:
--
资助国家:
德国
项目状态:
未结题
起止时间:
中文摘要
时间连续δ - σ adc受时钟抖动的影响,因为时钟边缘控制DAC的脉冲宽度,从而直接干扰反馈信号。为了减少时钟抖动的影响,今天主要使用开关电容,也与电阻(SCR-DAC)或多位dac结合使用。缺点是较高的转换速率要求和较高的电路复杂性。另一种建议是基于SC积分器,它将参考电荷与在时钟周期内集成的参考电流进行比较,并由此导出用于抖动补偿的校正信号。这里的关键是kT/ c噪声和电荷注入与时钟抖动的小绝对值相比。此外,该方法基于开关电容,这在连续时间δ - σ ADC中实际上是不可取的。本课题研究并实现了用有源方法对连续时间δ - σ adc中时钟抖动的影响进行连续时间补偿。该原理是基于DAC基准的交替上下集成和在几个时钟周期内集成值的比较。在比较的基础上,产生一个校正信号,该信号在随后的时钟相位馈送到积分器中,从而补偿时钟抖动带来的误差。该方法的优点是在时钟周期内连续积分,因此对补偿电路中的kT/ c噪声和电荷注入的灵敏度较低。只有配上补偿电路,使其本身不受明显的干扰和噪声的影响,才能对时钟抖动进行有源补偿。
英文摘要
Time-continuous delta-sigma ADCs are affected by clock jitter because the clock edges control the pulse width of the DAC and thus directly disturb the feedback signal. To reduce the influence of the clock jitter today mainly switched capacitors, also in conjunction with resistors (SCR-DAC), or multi-bit DACs are used. The disadvantage are higher slew rate requirements respectively a higher circuit complexity. Another proposal is based on an SC integrator, which compares a reference charge with a reference current integrated over the clock period and derives therefrom a correction signal for the jitter compensation. Critical here is the kT/C-noise and the charge injection compared to the small absolute value of the clock jitter. Moreover, the method is based on a switched capacitance, which is actually undesirable in continuous time delta-sigma ADC.In the project, a continuous-time compensation of the influence of the clock jitter in continuous-time delta-sigma ADCs with an active method is to be researched and realized. The principle is based on alternately up and down integration of the DAC reference and comparison of the integrated values over several clock periods. Based on the comparison, a correction signal is to be generated, which is fed into the integrator in subsequent clock phases and thus compensates for the error from the clock jitter. The advantage of this method is the successive continuous-time integration over the clock periods and thus a lower sensitivity to kT/C-noise and charge injection in the compensation circuit. Only with a compensation circuit, which itself is not subject to significant interference and noise, active compensation of the clock jitter can work.
期刊论文(0)
专著(0)
科研奖励(0)
会议论文
Delta-Sigma-ADC with dynamic clock control
-
批准号:391630368
-
项目类别:Research Grants
-
资助金额:$0.0万
-
财政年份:2017
-
负责人:Professor Dr.-Ing. Dirk Killat
-
依托单位:
Nyquist-Rate AD-Converters with Signal Dependent Sampling Rate
-
批准号:250702138
-
项目类别:Research Grants
-
资助金额:$0.0万
-
财政年份:2014
-
负责人:Professor Dr.-Ing. Dirk Killat
-
依托单位:
Analyse und Entwurf von integrierter CMOS Hochvoltelektronik in Niedervolttechnologien
-
批准号:207214355
-
项目类别:Research Grants
-
资助金额:$0.0万
-
财政年份:2011
-
负责人:Professor Dr.-Ing. Dirk Killat
-
依托单位:
国内基金
海外基金
高频数据波动率统计推断、预测与应用
-
批准号:71971118
-
项目类别:面上项目
-
资助金额:50.0万元
-
批准年份:2019
-
负责人:孔新兵
-
依托单位:
星载连续波合成孔径雷达信号处理方法研究
-
批准号:61172122
-
项目类别:面上项目
-
资助金额:55.0万元
-
批准年份:2011
-
负责人:王宇
-
依托单位:
连续化悬浮燃烧合成硅基陶瓷粉体的应用基础研究
-
批准号:50372074
-
项目类别:面上项目
-
资助金额:24.0万元
-
批准年份:2003
-
负责人:李江涛
-
依托单位: