Research on False Test Avoidance for LSI Yield Improvement

在VLSI测试中，测试输入数据往往会导致较高的开关活跃度，从而导致IR下降，从而导致信号传播延迟。已经表明，10%的电源电压降可能会使路径延迟增加15%。这种延迟增加通常会导致在捕获模式下将故障测试响应加载到触发器中。因此，在捕获模式下减少测试感应的开关活动尤为重要。这项研究致力于通过减少测试诱导的开关活动来解决成品率损失问题。本研究的成果如下：一、基本技术提出了一种处理深亚微米电路中的中间故障电压的技术。此外，还开发了一种结合编译代码和事件驱动技术来加速故障模拟的方法。II.全速测试技术为了提高测试质量，需要检测两个同步时钟域之间存在的故障。提出了一种跨时钟域全速测试控制器，既可以用于基于ATE的外部测试，也可以用于BIST。III.X位识别技术已经开发了几种技术来从完全指定的测试集中识别无关位(X位)，而不会造成任何故障覆盖损失。除了故障覆盖之外，还可以保留小延迟检测能力。IV.X填充技术已经提出了确定测试立方体中X位的逻辑值的几种技术，以使得到的测试集具有较低的开关活动性。无论是单次捕获方案还是双捕获方案，这些技术都可以减少IR-Drop。此外，所有单元(FF和门)的开关活动都可以被瞄准。V.低功耗测试生成技术为了进一步减少捕获开关活动，我们提出了一种ATPG方法，用于直接生成用于低测试功率目的的逻辑位。对于这种低功耗测试生成，引入了一个新的概念，称为捕获-冲突(C-Conflicent)。

In VLSI testing, test input data often causes high switching activity, which results in IR-drop, and thus signal propagation delay. It has been shown that a 10% supply voltage drop may increase path delay by 15%. This delay increase often causes faulted test response to be loaded into flip-flops in capture mode. As a result, it is especially important to reduce test-induced switching activity in capture mode. This research was focused on solving the yield loss problem by reducing test-induced switching activity. The achievements of this research are as follows:I. Basic TechniquesA technique for handling intermediate faulty voltages in a deep-submicron circuit has been proposed. In addition, a method for speeding up fault simulation by using both complied-code and event-driven techniques have been developed.II. At-Speed Test TechniquesFaults existing between two synchronous clock domains need to be detected in order to improve test quality. We proposed a inter-clock-domain at-speed test controller, which can be used in both ATE-based external test and BIST.III. X-Bit Identification TechniquesSeveral techniques for identifying don't care bits (X-bits) from a fully-specified test set without any fault coverage loss have been developed. In addition to fault coverage, the small-delay detection capability can also be preserved.IV. X-Filling TechniqueSeveral techniques for determining logic values for X-bits in test cubes so that the resulting test set has lower switching activity have been proposed. These techniques can reduce IR-drop for either a single-capture scheme or a double-capture scheme. In addition, switching activity at all cells (FFs and gates) can be targeted.V. Low-Power Test Generation TechniquesIn order to further reduce capture switching activity, we proposed an ATPG method for directly generating logic bites for the purpose of low test power. Anew concept, called capture-conflict (C-conflict), was introduced for this low-power test generation.