HYPNOS - Co-Design of Persistent, Energy-efficient and High-speed Embedded Processor Systems with Hybrid Volatility Memory Organisation

HYPNOS项目探索新兴的非易失性存储器（NVM）技术如何不仅可以在现代嵌入式处理器架构中有益地取代主存储器，但也可能是一个或多个级别的缓存层次结构，甚至寄存器，以及如何优化这种混合易失性存储器层次结构，以便为众多应用程序提供高速和低能量的权衡，同时以简单有效的方式提供数据结构和处理状态的持久性。一方面，为物联网设备出现的完全非易失性（存储器）处理器（NVPs）的写入时间较低，并且耐久性比SRAM等技术低几个数量级，因此无法在GHz速度下运行。另一方面，现有的NVM主存计算机解决方案需要程序员通过缓存层次显式地持久化数据结构。HYPNOS（以希腊睡眠之神命名）通过采用硬件/软件协同设计方法系统地解决了这种交织在一起的性能/耐久性/可编程性差距：我们的研究包括混合NVM内存处理器架构的设计空间探索技术。速度和能耗，包括混合（混合易失性）寄存器和缓存级设计，b)通过检查点和恢复功能的低成本和低延迟控制单元（硬件）设计，为（非事务性）程序提供指令级持久性，例如，在瞬时电源故障的情况下；c)在多核HyPNOS系统上提供应用程序程序员（软件）持久性控制，用于用户定义的检查点和从这些错误和其他错误或访问冲突中恢复，这些错误或访问冲突由大小有限的硬件事务性内存（HTM）支持。d)探索的处理器架构设计和不同类型的NVM技术将系统地评估可实现的速度和能量增益，以及测试共同设计的备份和恢复机制，例如，唤醒延迟等，使用基于gem5的多核仿真平台和使用带有HTM指令扩展的ARM处理器。作为基准，从i)简单数据结构，ii)传感器（外围设备）i /O到最后iii)事务性数据库应用程序的层次结构将被协作地调查和评估。

Project HYPNOS explores how emerging non-volatile memory (NVM) technologies could beneficially replace not only main memory in modern embedded processor architectures, but potentially also one or multiple levels of the cache hierarchy or even the registers and how to optimize such a hybrid-volatile memory hierarchy for offering high speed and low energy tradeoffs for a multitude of application programs while providing persistence of data structures and processing state in a simple and efficient way. On the one hand, completely non-volatile (memory) processors (NVPs) that have emerged for IoT devices are known to suffer from low write times of current NVM technologies as well as by orders of magnitude lower endurance than, e.g., SRAM, thus prohibiting an operation at GHz speeds. On the other hand, existing NVM main memory computer solutions suffer from the need of the programmer to explicitly persist data structures through the cache hierarchy. HYPNOS (Named after the Greek god of sleep) systematically attacks this intertwined performance/endurance/programmability gap by taking a hardware/software co-design approach:Our investigations include techniques fora) design space exploration of hybrid NVM memory processor architectures} wrt. speed and energy consumption including hybrid (mixed volatile) register and cache-level designs,b) offering instruction-level persistence for (non-transactional) programs in case of, e.g., instantaneous power failures through low-cost and low-latency control unit (hardware) design of checkpointing and recovery functions, and additionally providingc) application-programmer (software) persistence control on a multi-core HyPNOS system for user-defined checkpointing and recovery from these and other errors or access conflicts backed by size-limited hardware transactional memory (HTM).d) The explored processor architecture designs and different types of NVM technologies will be systematically evaluated for achievable speed and energy gains, and for testing co-designed backup and recovery mechanisms, e.g., wakeup latencies, etc., using a gem5-based multi-core simulation platform and using ARM processors with HTM instruction extensions.As benchmarks, the hierarchyfrom i) simple data structures, ii) sensor (peripheral device) I/O and finally iii) transactional database applications shall be collaboratively investigated and evaluated.