Theory and design of fault tolerant integrated systems

该研究项目的目的是为容错集成系统建立基础，该系统具有并行纠错和自我重新配置的潜力，以排除故障部件。本项目的主要贡献总结如下：1.并行计算系统的在线故障检测与诊断：提出了基于算法的容错系统分析与综合的图论模型。在该模型的基础上，提出了几种single-fault-locatable/double-fault-detectable系统的检查方案和操作/检查映射方案。脉动阵列的在线纠错并行计算：提出了一种基于时空混合空间三模冗余的容错脉动阵列。在该方案中，不仅计算和通信都是倍增的，而且需要链路共享来降低其链路复杂度。提出了保证高可靠性和可调度性的链路共享方案。基于WSIS的容错网络计算重构：提出了环面网络的重构算法。文中还研究了该重构算法所需的充分的硬件(互连资源)冗余，扩展到控制密集型应用以及在线正确性和可重构性的融合是未来需要解决的问题。

The aim of this research project is to establish bases for fault tolerant integrated systems which have the potential to correct errors concurrently and to reconfigure themselves so as to exclude faulty components. The major contributions of this project are summarized in the following.1. On-line fault detection and diagnosis for parallel computing systems : We have proposed graph-theoretic model for analysis and synthesis of algorithm-based fault-tolerance systems. Based on this model, we have developed several checking schemes and operation / checking mapping schemes for single-fault-locatable/double-fault-detectable systems.2. On-line error correctable parallel computing on systolic arrays : Fault tolerant systolic array based on Triple Modular Redundancy in mixed spatial-temporal space has been proposed. In this scheme, not only computations but also communications are multiplicated, and link sharing is necessary to reduce its link complexity. Link sharing scheme which guarantees high reliability and schedulability has been also proposed.3. Reconfiguration for fault tolerant network computing on WSIs : Reconfiguration algorithm for torus networks has been proposed. Necessary and sufficient hardware(interconnection resource) redundancy required for this reconfiguration algorithm has been also investigated.Extension to control-intensive applications and a fusion of on-line correctability and reconfigurability are problems to be tackled in future.