Studies on High-Speed Transaction Machines Utilizing Hardware Concurrency Control Mechanisms

在该项目的第一年，开始了对体系结构和并发控制机制的基本调查。在接下来的一年中，对热点数据的并发控制进行了仿真研究，并对备份机制进行了硬件设计。主要研究成果如下：1）在响应时间受限的可串行性条件下，对异构数据和长事务的并发控制机制进行了理论研究; 2）设计了一种新的数据库系统中热点数据和非热点数据分别处理的并发控制方法，3）研究了并行事务模型的并发控制机制及其硬件实现。该研究揭示了这种架构中死锁增加的问题。提出了一种解决方案，并完成了其硬件设计。4）设计了一种连续备份存储器。由于热点数据的备份成本昂贵，因此开始研究和开发不会减慢系统操作的同步硬件备份机制。设计了一个连续备份的磁盘单元。在目标系统的设计中集成了这些机制，使得备份开销小。5）设计了一个硬件日志系统。由于数据库操作的日志记录占用了某些系统总操作时间的近50%，因此CPU总线的硬件监视器正在开发中。

In the first year of this project, basic surveys on architectures and concurrency control mechanisms were initiated. In the next year, concurrency control for hotspot data were studied through simulations, and the hardware for the backup mechanism was designed. The final year was spent for implementation of the machine and publication of the results.The major results are summarized as follows.1) Theoretical studies were carried out on concurrency control mechanisms which can handle heterogeneous data and long term transactions under the serializability restricted with response time.2) A new method was designed for concurrency control in database systems handling hotspot data and non-hotspot data separately, which had not been studied before.3) A concurrency control mechanism for the parallel transaction model and its hardware implementation were studied. This research disclosed the problem of increased deadlocks in this architecture. A measure for this effect was proposed, and its hardware design was completed.4) A continuously backuped memory was designed. Since the backup cost for hotspot data is expensive, research and development was initiated for a simultaneous hardware backup mechanism which does not slow down system operations. A continuously backuped disk unit was also designed. These mechanisms were integrated in the design of the target system which requires low overhead for backup.5) A hardware logging system was designed. Since logging of database operations occupies nearly 50% of the total operation time of some systems, the hardware monitor for CPU buses is now under development.