Logic synthesis using EXOR gates

自动逻辑合成工具广泛应用于大规模集成电路设计。大多数逻辑合成工具使用与或门作为基本逻辑元件。算术和纠错电路可以用更少的门来实现，如果输出门和与或门可用。这种电路可以由AND-EXOR双电平电路衍生而来。因此，异或积和表达式（ESOPs）的最小化是非常重要的，它对应于两级电路的AND-EXOR的最小化。在实现随机生成函数和对称函数时，ESOPs比sop需要更少的产品。为了实现6个变量的任意函数，ESOP只需要16个产品，而SOP需要32个产品。虽然有一类函数的员工持股计划的实现需要更多的生产sop，但员工持股计划是高效逻辑设计的重要工具。通过在输入端添加解码器（如：1），可以减少与或双电平电路中的产品数量。例如，与或（AND-OR）的PLAs（更多的二进制解码器）。以类似的方式，在AND-EXOR双电平电路中，可以通过在输入端添加解码器来减少产品的数量。例如，带两位解码器的AND-EXOR PLAs)。我们比较了数字乘积和文字，以表示8输入的算术函数，这些算术函数由带有1位和2位解码器的and - or电路和and - exor电路组成，其中1位解码器生成真变量和互补变量。基于ESOPs的电路比基于SOPS的电路需要更少的门。带解码器的AND-EXOR电路的最小化可以通过带多值输入的esop的最小化来实现。第一个结果是EXMIN2，这是一种用于具有多值输入的AND-EXOR表达式的启发式简化算法。该算法以迭代减少ESOPs中的产品数量为第一目标，再以迭代减少字面数为第二目标。实验结果表明，与标准操作程序相比，ESOPs通常需要更少的产品和连接来表示算术函数。第二个结果是AND-OR-EXOR电路的设计方法。在大多数技术中，exor比ORs更昂贵。为了降低成本，我们开发了一种方法，在不增加产品数量的情况下，将esop中的一些exor替换为or。少

Automatic logic synthesis tools are extensively used in LSI design. Most logic synthesis tools use AND and OR gates as basic logic elements. Arithmetic and error correcting circuits can be realized with many fewer gates if EXOR gates are available as well as AND and OR gates. Such circuits can be derived from AND-EXOR two-level circuits. So the minimization of Exclusive-OR sum-of-products expressions(ESOPs), which corresponds to the minimization of AND-EXOR two-level circuits, is important. ESOPs require fewer products than SOPs to realize randomly generated functions and symmetric functions. To realize an arbitrary function of 6 variables, an ESOP requires only 16 products, whereas an SOP requires 32 products. Although there exists a class of functions whose ESOP realizations require more production SOPS, the ESOP's are important tool in efficient logic design. The number of products in AND-OR two-level circuits can be reduced by adding decoders to the inputs(i. e., AND-OR PLAs with t … More wo-bit decoders). In a similar way, the number of products in AND-EXOR two-level circuits can be reduced by adding decoders to the inputs(i. e., AND-EXOR PLAs with two-bit decoders). We compared the number products and literals to represent arithmetic functions of 8-inputs by AND-OR circuits and AND-EXOR circuits with one and two-bit decoders, where a one-bit decoder generates true and complemented variables. Circuits based on ESOPs required fewer gates than the ones based on SOPS. The minimization of AND-EXOR circuits with decoders can be done by the minimization of ESOPs with multiple-valued inputs.The first result is EXMIN2, a heuristic simplification algorithm for AND-EXOR expression with multiple-valued inputs. The algorithm iteratively reduces the number of the products in ESOPs as the first objective, and then reduces the number of the literals as the second objectives. Experimental results show that ESOPs usually require fewer products and connections than SOPs to represent arithmetic functions. The-second result is a design method for AND-OR-EXOR circuits. In the most technologies, EXORs are more expensive than ORs. To reduce the cost, we developed a method to replace some of the EXORs with ORs in ESOPs without increasing the number of the products. Less