Graphene Based Triple-Gate-Platforms for Novel Tunnel Field-Effect Transistors

与常规场效应晶体管(FET)相比，隧道FET(TFET)允许在室温下实现低于60 mV/十的反向亚阈值斜率。因此，TFET具有超低功耗的潜力。理想情况下，TFET器件中的载流子传输仅依赖于玻尔兹曼体系中的带间隧道和能量过滤。通过将单个电势施加到近距离的掩埋栅电极，可以静电地调整沿半导体沟道区的不同能带配置，以控制隧穿概率。然而，为了获得沿沟道均匀的电场分布，掩埋和互绝缘电极(掩埋三栅极，BTG)的制造对于平面工艺来说可能是具有挑战性的。在这个项目中，我们提出了一种基于石墨烯的BTG平台的新概念，用于TFET的表征。这一概念的优点是至少有一个栅电极是由几乎原子薄的石墨烯层制成的，这使得能够制备垂直堆积的石墨烯/氧化物薄层异质结构。提出的概念允许尖锐的静电掺杂分布和非常窄的能带跃迁。这进而增加了带间隧道概率，并在TFET特性中提供了非常陡峭的亚阈值斜率。我们计划集成低维WS2来制造概念验证型TFET。这些设备将通过先进的表征技术进行分析，包括基于高分辨率光电子显微镜(PEEM)的专用手术中方法。其他表征技术包括二维拉曼光谱、原位X射线光电子能谱(XPS)和在8K至500K温度范围内的电学表征。所提出的设计是通用的，并允许任何半导体一维或二维材料的集成。

Compared to conventional field-effect transistors (FETs), tunnel-FETs (TFETs) allow for inverse sub-threshold slopes below 60 mV/decade at room temperature. Therefore, TFETs have the potential of ultra low-power consumption. Ideally, carrier transport in TFET devices only depends on band-to-band tunnelling and energy filtering in the Boltzmann regime. By applying individual potentials to buried gate electrodes in close proximity, different band configurations along a semiconductor channel region can be electrostatically adjusted to control the tunneling probability. However, to achieve a homogenous electric field distribution along the channel, fabrication of buried and mutually insolated electrodes (buried triple-gate, BTG) can be challenging for planar processes. In this project we propose a novel concept of a graphene-based BTG platform for TFET characterization. The advantage of this concept is that at least one gate-electrode is made of an almost atomically thin graphene layer, which enables fabrication of thin vertically stacked graphene/oxide-heterostructures. The proposed concept allows for sharp electrostatic doping profiles and very narrow band transitions. This in turn, increases the band-to-band tunnelling probability and provides very steep subthreshold slopes in TFET characterization. We plan to integrate low-dimensional WS2 for fabrication of proof-of-concept TFETs. The devices will be analyzed by advanced characterization techniques, including a dedicated in operando method based on high resolution photoemission electron microscopy (PEEM). Other characterization techniques include 2D Raman Spectroscopy, in situ X-ray photoelectron spectroscopy (XPS), and electrical characterization in a temperature range between 8 K and 500 K. The proposed design is versatile and allows for integration of any semiconducting 1D- or 2D-material.