Development of a Computer Specific to LSI Geometrical Processing
Development of a Computer Specific to LSI Geometrical Processing
批准号:
04555078
负责人:
TAMARU Keikichi
金额:
$10.18万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
财政年份:
1992
资助国家:
日本
项目状态:
已结题
起止时间:
1992 至 1994
中文摘要
本研究的目的是开发一种能够快速处理几何图形的专用计算机。几何图形处理是当前大规模集成电路设计的基本功能。它包括逻辑、拓扑和几何运算以及面积/长度计算。本研究旨在解决当前大规模集成电路设计过程中的瓶颈问题。本研究的结果如下1。大规模集成电路设计规则校验(DRC)中并行处理的加速专用于LSI dr3的计算机系统的开发。一种基于功能划分的DRC方法。功能存储器型并行处理器的研制。我们构建了一个计算机系统来评估上述结果。控制所有处理器元件(称为工人)的主计算机是使用68040个处理器的标准工程工作站。我们开发了四个全新的工人。工作器使用双端口内存模块同时执行数据输入和输出。工作中的DRC处理单元是一个单板计算机,由一个称为M32/100的CPU组成。并开发了控制系统和执行DRC的软件包。这个有两个工人的系统执行DRC的速度比只有一个工人的系统快两倍。
英文摘要
The objective of this research is that we should develop a specific computer which performs geometrical-figure processing very rapidly. The geometrical-figure processing is the primitive function in the current LSI design. It comprises logical, topological and geometrical operations and also area/length calculation.This research aimed to dissolve the bottle-neck in the current LSI design process by that specific computer.The results of this research are as follows1.Acceleration of parallel processing in LSI design rule check (DRC)2.Development of a computer system specific to LSI DRC3.A method of DRC by functional partitioning.4.Development of a functional memory type parallel processor.We constructed a computer system to evaluate the above results. A host computer which controls all processor elements (called workers) is a standard engineering work station using 68040 processors. We developed four brand-new workers. The worker performs data input and output simultaneously using two-port memory modules. The DRC processing unit in the worker is a single-board computer which comprises a CPU called M32/100. And also we developed software packages which control the system and performs DRC.This system with two workers performs DRC twice faster than that with a single worker.
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K.Tamaru: "The Trend of Functional Memory Development" IEICE Trans.Electron.E76-C. 1545-1554 (1993)
K.Tamaru:“功能存储器发展趋势”IEICE Trans.Electron.E76-C。
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通讯作者:
K.Kobayashi: ""A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture"" IEICE Trans.Electron.Vol.E76-C,No.7. 1151-1158 (1993)
K.Kobayashi:“一种位并行块并行功能存储器型并行处理器架构””IEICE Trans.Electron.Vol.E76-C,No.7。
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K.Koboyashi: "A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture" IEICE Trans.Electron.E76-C. 1151-1158 (1993)
K.Koboyashi:“一种位并行块并行功能存储器类型并行处理器架构”IEICE Trans.Electron.E76-C。
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田丸 啓吉: "“新しい機能メモリー演算機能を持つメモリー"" 1994年電子情報通信学会秋季全国大会講演論文集. No.GC-2-6. 261-262 (1994)
Keikichi Tamaru:“‘具有新的功能性存储器算术功能的存储器’”1994 年秋季全国电子、信息和通信工程师学会会议记录,No.GC-2-6 (1994)。
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作者:
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通讯作者:
K.Tamaru: "The Trend of Functional Memory Development" IEICE Trans.Electronics. E76-C. 1545-1554 (1993)
K.Tamaru:“功能存储器发展趋势”IEICE Trans.Electronics。
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共 12 条
Development of a Computing System by a Functional Memory Type Parallel Processor.
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批准号:07558039
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项目类别:Grant-in-Aid for Scientific Research (A)
-
资助金额:$5.95万
-
财政年份:1995
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负责人:TAMARU Keikichi
-
依托单位:
Effective Design Methodology for Analog LSIs that Acquires and Reuses Design
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批准号:05452197
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项目类别:Grant-in-Aid for General Scientific Research (B)
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资助金额:$4.61万
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财政年份:1993
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负责人:TAMARU Keikichi
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依托单位:
Studies on Functional Memory Type Parallel Processor Architectures and Their Massively Parallel Algorithms.
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批准号:02452160
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项目类别:Grant-in-Aid for General Scientific Research (B)
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资助金额:$4.29万
-
财政年份:1990
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负责人:TAMARU Keikichi
-
依托单位:
Development of an Integrated Analog-Digital CAD System
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批准号:01850076
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项目类别:Grant-in-Aid for Developmental Scientific Research
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资助金额:$9.47万
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财政年份:1989
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负责人:TAMARU Keikichi
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依托单位:
Studies on a Hierarchical CAD System for Analog LSIs
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批准号:62460127
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项目类别:Grant-in-Aid for General Scientific Research (B)
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资助金额:$4.99万
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财政年份:1987
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负责人:TAMARU Keikichi
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依托单位: