A high performance on-chip data transfer technique using pulse modulation signals

为了提高片上数据传输系统的比特率和功率效率，开发了使用脉冲调制信号的数据收发器电路。脉冲相位调制（PPM）系统与脉冲宽度调制（PWM）系统相比具有更高的性能。然而，PPM需要精确的相位同步电路，这消耗大量的功率和芯片面积。采用250 MHz、4相延迟锁相环技术设计了PWM数据收发电路，获得了1 ns的时间分辨率。它以低功耗实现了1Gbits/sec的数据传输速率。对于门阵列的实现，开发了仅利用逻辑门的PWM收发器电路。采用硬件描述语言（HDL）对这些收发器电路进行描述，并利用逻辑综合工具进行综合。通过Verilog-XL逻辑仿真和HSPICE电路仿真对电路进行了评估。PWM收发器测试芯片采用0.5mum CMOS工艺设计。利用标准单元设计工具设计了掩模版图。利用任意波形发生器和逻辑分析仪实现了PWM收发器1 ns定时精度和误码率的测量。测试芯片的测试结果表明，最高时钟频率和定时精度与仿真结果基本一致。

In order to improve a bit rate and power efficiency for on-chip data transfer systems, data transceiver circuits using pulse modulation signals were developed. A pulse phase modulation (PPM) system has higher performance comparing with a pulse width modulation (PWM). However, PPM requires precision phase synchronizing circuit which consumes much power and chip area. A PWM data transceiver circuits were designed by using a 250-MHz, 4-phase delay locked loop technique, and a 1ns time resolution was obtained. It realizes 1Gbits/sec data rate with low power dissipation. For implementations by gate arrays, a PWM transceiver circuit utilizing only logic gates was developed. These transceiver circuits were described by hardware description language (HDL), and synthesized by logic synthesis tools. The circuits were evaluated by logic simulation (Verilog-XL) and circuits simulation (HSPICE). The PWM transceiver test chip was designed using a 0.5mum CMOS process. A Mask Layout was designed by standard cell design tools. A measurement technique for a 1ns timing accuracy and a bit error rate of the PWM transceiver was achieved using an arbitrary wave from generator and a logic analyzer. The measurements results of the test chip shows that maximum clock frequency and timing accuracy are almost as the same as the simulation results.