Fabrication of PZT thin films using digital-MOCVD method and its application for electronic devices

近年来，铅基钙钛矿结构的铁电薄膜作为动态随机存取存储器(DRAM)和铁电随机存取存储器(FeRAMs)的电容介质膜以及金属-铁电-半导体(MFS)栅极结构的铁电栅场效应管(FET)的栅绝缘体材料受到了广泛的研究。特别值得一提的是，MFS-FET具有非易失性、高开关速度、高集成度、无需存储电容等优点，有望成为未来存储器件的主要候选者之一。然而，对于直接在硅衬底上制备铁电薄膜，由于它们之间的互扩散和晶格失配，在形成铁电/硅界面方面一直存在困难，因此几乎没有令人满意的结果。在这项研究中。制备并表征了铁电栅场效应晶体管的主要器件之一--PZT/MgO/Si(001)叠层结构。在最高加工温度为480ﾟC的PZT(001)/MgO(001)/Si(001)叠层结构中，用theta-2theta和二维X射线衍射法证实了PZT[100]//MgO[100]//Si[110]的全外延关系。全外延关系不影响PZT和Si的电学性能。特别是对于氧化镁/硅界面，可以通过铁电栅场效应管中的栅极电压来控制硅的表面电势。

Recently, ferroelectric thin films such as Lead based perovskite structure have been actively studied as one of the promising materials for capacitor dielectric films in dynamic random-access memories (DRAMs) and ferroelectric random-access memories (FeRAMs), and for gate insulators in ferroelectric-gate FETs with metal-ferroelectric-semiconductor (MFS) gate structure. In particular, MFS-FET is expected to be one of the leading candidates for the future memory devices because of its non-volatility, high switching speed, high integration without storage capacitors, and so on. However, there have been few satisfactory results regarding fabrication of ferroelectric thin films directly on Si substrates, because there have been difficulties in the formation of ferroelectric/Si interfaces due to interdiffusions and lattice mismatches between them. ln this research. Pb(Zr, Ti)O_3 (PZT)/MgO/Si(0O1) stacked structure, which is one of the principle components of ferroelectric-gate FETs, has been fabricated and characterized. Using both the theta-2theta and the 2-dimensional X-ray diffraction (XRD) method, the fully epitaxial relationship of PZT[100]//MgO[100]//Si[110] has been confirmed in the PZT(001)/MgO(001)/Si(001) stacked structure fabricated with the maximum processing temperature of 480ﾟC.The fully epitaxial relationship causes no affection on the electrical properties of PZT and Si. Especially for MgO/Si interfaces, itwould make possible to control the surface potential of Si by the gate voltages in ferroelectric-gate FETs.