Hardware Synthesis of High-speed Network Monitors

由于最近互联网的进步，我们需要高速的网络监视器，每秒可以观察数百万个数据包。提出了一种由LOTOS语言描述的高速网络监控器的形式化规范综合硬件电路的方法，该方法将给定的网络监控器建模为并发EFSM，并使用LOTOS中的多会合来描述它们之间的数据交换。根据监控项目和网络速度，我们必须推导出不同的硬件电路。对于这样的参数值，该方法可以自动选择合适的硬件模块，并调整派生硬件组件的参数值。我们开发了一个工具，可以从给定的规范生成对应的RT级VHDL语言规范，并根据得到的VHDL语言描述综合出一个FPGA电路。通过实验，我们已经证实了所生成的电路具有足够的速度来监控千兆以太网中的数据包。

Due to recent progress of the Internet, We need high-speed network monitors which can observe millions of packets per second. This research proposes a technique to synthesize hardware circuits from formal specifications of high-Speed network monitors described in LOTOS language.In the proposed method, a given network monitor is modeled as concurrent EFSMs, and data exchange among them is specified using multi-rendezvous in LOTOS. Depending on monitoring items and network speeds,We must derive different hardware circuits. For such parameter values, the proposed method can automatically select suitable hardware modules and adjust parameter values of the derived hardware component. We have developed a tool to generate the corresponding RT-level VHDL Specification from a given specification, and synthesize an FPGA circuit from the derived VHDL description. From our experiments, We have confirmed that the generated circuits have enough speeds for monitoring packets in Gigabit Ethernet.