Modeling of GaN-based Electron Devices

近年来，GaN基场效应晶体管因其在高功率、高温微波器件中的潜在应用而受到人们的极大关注。然而，即使漏极电压或栅极电压突然改变，也经常观察到缓慢的电流瞬变。这被称为漏极滞后或栅极滞后，并且在电路应用中是有问题的。慢瞬变意味着直流I-V曲线和交流I-V曲线变得非常不同，导致可用的交流功率低于直流工作时的预期功率。这在GaN器件领域被称为功率骤降或电流崩溃。这些被认为与陷阱相关，并且有许多关于这些现象的实验工作报道。但是，GaN基场效应晶体管的理论研究报道很少，因此，本文采用半绝缘缓冲层的三能级补偿模型，对GaN MESFET进行了二维瞬态模拟，其中浅施主、深施主和深施主分别作为半绝缘缓冲层和深施主，而浅施主和深施主分别作为半绝缘缓冲层和深施主。 ...更多信息 考虑了受体。由瞬态特性导出了准脉冲I-V曲线。已经表明，当漏极电压升高时，漏极电流过冲稳态值，并且当漏极电压降低时，漏极电流保持在低值，显示漏极滞后行为。这是由深施主的电子俘获和电子发射过程解释的。漏极滞后已被证明成为电流崩溃的原因，虽然一些栅极滞后也被视为由于在缓冲层中的深层次。当缓冲层中的深受主密度较高时，以及当关断状态漏极电压较高时，电流崩溃已被示出为更显著，因为捕获效应变得更显著。这些缓冲俘获效应可类似于AlGaN/GaN HEMT中的未掺杂GaN层中的俘获效应。得出的结论是，为了最大限度地减少GaN FET中的电流崩塌，缓冲层中的（深）受主密度应该被制得较低。少

Recently, GaN-based FETs have received great interest because of their potential applications to high power and high temperature microwave devices. However, slow current transients are often observed even if the drain voltage or the gate voltage is changed abruptly. This is called drain lag or gate lag, and is problematic in circuit applications. The slow transients mean that the dc I-V curves and the ac I-V curves become quite different, resulting in lower ac power available than that expected from the dc operation. This is called power slump or current collapse in the GaN-device field. These are regarded as trap-related, and there are many experimental works reported on these phenomena. But, few theoretical works have been reported for GaN-based FETsTherefore, in this work, two-dimensional transient simulations of GaN MESFETs have been performed in which a three level compensation model is adopted for the semi-insulating buffer layer where a shallow donor a deep donor, and a deep acc … More eptor are considered. Quasi-pulsed I-V curves have been derived from the transient characteristics. It has been shown that when the drain voltage is raised, the drain current overshoots the steady-state value, and when it is lowered, the drain current remains at a low value, showing drain-lag behavior. These are explained by the deep donor's electron capturing and electron emission processes. The drain lag has been shown to become a cause of current collapse, although some gate lag is also seen due to deep levels in the buffer layer. The current collapse has been shown to be more pronounced when the deep-acceptor density in the buffer layer is higher and when the off-state drain voltage is higher, because the trapping effects become more significant. These buffer-trapping effects may be similar to trapping effects in an undoped GaN layer in AlGaN/GaN HEMTs. It is concluded that to minimize the current collapse in GaN FETs, the (deep) acceptor density in the buffer layer should be made low. Less