Super-Low-Operating-Voltage Dependable SRAM Using Total Variability Suppression Effects in FD-SOI

我们提出了一种用于FD-SOI SRAM的衬底偏置控制方案，该方案抑制了管芯间的可变性，并提出了一种可以动态补偿其管芯内可变性的7 T/14 T（7-晶体管/14-晶体管）存储单元。所提出的衬底偏置控制电路自动检测管芯间阈值电压变化，然后最大化存储器单元的读/写裕度以提供衬底偏置。我们证实了一个150纳米486 kb的FD-SOI SRAM工作在0。42 V，其中FS转角可以与0.为了验证7 T/14 T可靠存储单元，我们制作了一个150 nm 576 kb FD-SOI SRAM。14 T可靠模式在14 T信元中分配一个比特，并改善其误码率。在我们的测量中，在14 T可靠模式下，最小保持电压和最小工作电压分别比7 T正常模式降低了150 mV和320 mV。

We proposed a substrate bias control scheme for an FD-SOI SRAM that suppresses inter-die variability and a 7T/14T(7-transistor/14-transistor) memory cell that can be dynamically compensate its intra-die variability. The proposed substrate bias control circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 150-nm 486-kb FD-SOI SRAM operates at 0. 42 V, in which an FS corner can be compared as much as 0. 14 V. For the 7T/14T dependable memory cell verification, we fabricated a 150-nm 576-kb FD-SOI SRAM. The 14T dependable mode allocates one bit in a 14T cell and improves its bit error rate. In our measurements, the minimum retention voltage and the minimum operating voltage were reduced by 150 mV and 320 mV in the 14T dependable mode over the 7T normal mode, respectively.