Power Adjustment Testing for Next-Generation Low-Power LSI Circuits

在LSI测试中存在两个主要问题，即由于沿着敏化路径的过度延迟而降低测试良率和由于沿着敏化路径的不充分延迟而降低测试质量。在这项研究中，已经建立了一种新的方案，该方案动态调整敏感路径附近的区域功耗，以尽量减少其对测试产量和测试质量的影响。这种功率调整测试方案有望有助于提高测试成品率和测试质量。

There are two major problems in LSI testing, namely decreasing test yield due to excessive delay along sensitized paths and decreasing test quality due to inadequate delay along sensitized paths. In this research, a novel scheme has been established, which dynamically adjusts regional power dissipation in the neighborhood of sensitized paths to minimize its impact on test yield and test quality. This scheme of power adjustment testing is expected to contribute to higher test yield and better test quality.