Equivalence Checking for System-Level Designs Having Different Input-Output Timings

在这项工作中，嵌入式系统或VLSI的设计验证方法进行了研究。设计验证的目的是检查给定的设计是否正确，如果不正确，则提供失败模式。我们专注于两个设计的等价性检查。我们的验证目标是系统级设计，这是一个高度抽象的设计层次，并已成为近年来广泛应用。我们提出了等价性检查方法，可以处理给定的两个设计之间的不同的输入/输出时序。此外，我们还开发了一种方法来检测潜在的等效内部变量的设计。本文的目的是通过这些方法来提高系统级设计的等价性检验能力。

In this work, design verification methods for embedded systems or VLSIs are studied. The purpose of design verification is to check whether a given design is correct or not and provide failing patterns if incorrect. We focus on equivalence checking of given two designs. Our target of verification is system-level design, which is a highly abstracted design level and has become widely applied recently. We proposed equivalence checking methods that can deal with different input/output timings between given two designs. In addition, we have developed a method to detect potentially equivalent internal variables in designs. The purposed of this work is to improve the ability of equivalence checking for system-level designs by those proposed methods.