Communication analysis for Network-on-Chip

片上网络（NoC）是未来片上系统（SoC）高效设计的新范例，它通过组成数百个互连的IP块（如CPU和DSP核心）、特定应用硬件和大量内存来利用单个asic的数十亿晶体管容量。SoC设计人员面临的主要挑战是掌握在时序、面积和低功耗限制下，随着深亚微米效应（例如串扰、干扰）问题的增加，系统功能的大幅增加。片上网络是解决这些问题的一种很有前途的方法，它用分组路由网络取代全球线路和片上总线。其主要优点是通过引入结构良好的互连布局而不是长距离布线来减少电磁效应，以及通过使用动态分组路由而不是片上总线和直连网络来提供良好的可扩展性和网络利用率。片上分组路由体系结构的主要缺点是由于动态分组路由而大大降低了时间可预测性，因此NoC体系结构不适用于嵌入式实时应用的宽带宽。因此，本项目旨在通过研究新的分析和综合方法来确定通信的时间依赖性，计算自动网络生成的参数，并完善NoC通信协议的分析方法，从而消除这一问题。网络生成的参数计算包括组件放置以最小化通信延迟和共享通信资源的冲突，以及在设计时确定有效路由以保证满足给定时间约束的可预测时间。

Network-on-Chip (NoC) is a new paradigm to enable an efficient design of future Systems-onChip (SoC), which exploit the multi-billion transistor capacity of single ASICs by composing hundreds of interconnected IP blocks, such as CPU and DSP cores, application specific hardware and large amounts of memory. The major challenge for SoC designers is to master the strongly increased system functionality being accompanied by increasing problems of deep submicron effects (e.g. cross-talk, interference) under timing, area, and low power constraints. Networks-on-Chip are a promising approach to address these problems by replacing global wires and on-chip busses with packet routing networks. The main advantages are reduction of electro-magnetic effects by introducing a well-structured interconnection layout instead of long-distance wiring as well as providing a good scalability and network utilization by using dynamic packet routing instead of on-chip busses and direct networks. The major drawback of on-chip packet-routing architectures is the strongly decreased timing predictability, due to dynamic packet routing, so that NoC architectures are not applicable to a wide bandwidth of embedded real-time applications. Therefore, this project aims to eliminate this problem by investigating new analysis and synthesis methods to determine temporal dependencies for communications, to calculate parameters for automatic network Generation, and to refine analysis methods for NoC communication protocols. Parameter calculation for network Generation include the component placement to minimize communication latencies and conflicts on shared communication resources and the determination of efficient routing at design time in order to guarantee a predictable timing satisfying given timing constraints.