Studies on combined arithmetic circuits for high-speed digital signal processing

我们开发了组合算术电路的设计方法，将数字信号处理中出现的连续加减和乘法作为一个运算来执行，并开发了使用这些电路的高速计算方法。主要研究结果如下：1。设计了一种将数字信号处理中经常出现的连续加法、乘法和加法作为一个运算来执行的加乘加法器，并展示了它的应用。我们开发了一种新的高速平方根算法，该算法使用乘加器将连续的乘法和加法作为一个操作来执行。我们提出了一种利用带操作数修饰符的乘法器来生成操作数幂的新方法，如倒数、平方根、倒数平方根、倒数平方、倒数立方等。在假设从左到右输入到达的情况下，我们开发了一种理论上最优且在实践中非常有效的加法器。我们开发了两种用于密码系统中模量非常大的模除法的硬件算法。一种是基于扩展欧几里得算法，另一种是基于二进制GCD算法。我们已经开发了用于在功能存储器上执行算术运算的大规模并行算法，并开发了一种使用它们进行运动矢量检测的方法。

We have developed methods for designing combined arithmetic circuits which execute consecutive addition/subtractions and multiplications appearing in degital signal processing as one operation, and also developed high-speed computing method using these circuits. The main results are as follows :1. We have designed an add-multiply-adder which executes consecutive addition, multipli-cation and addition appearing often in degital signal processing as one operation, and shown its applications.2. We have developed a new high-speed square rooting algorithm using a multiply-adder which executes consecutive multiplication and addition as one operation.3. We have developed a new method for generating powers of an operand, such as recirocal, square root, reciprocal square root, reciprocal square, reciprocal cube and so on, using a multiplier with operand modifier.4. We have developed an adder which is optimal in theory and very efficient in practice, under the assumption of left-to-righ input arrival.5. We have developed two hardware algorithms for modular division with very large modulus which is required in cryptosystems. One is based on the extended Euclidean algorithm and the other is based on the binay GCD algorithm.6. We have developed massively parallel algorithms for executing arithmetic operations on a functional memory and have developed a method for motion vector detection using them.