Advanced discretisation strategies for atomistic nano CMOS simulation

愿景：这项概念验证研究的目的是研究如何利用计算力学的最新革命性进展来增强纳米互补金属氧化物半导体（CMOS）的建模。CMOS器件的尺寸正在积极地缩小到十纳米范围（百分之一微米）。预计到2018年，大规模生产的金属氧化物半导体场效应晶体管（MOSFET）的栅极长度将达到7纳米（2003年版的国际半导体技术路线图）。建模和仿真提供了对现代半导体器件和电路操作的深入了解，并大大降低了开发成本和上市时间。纳米尺度面临着重大的困难与统计变异性从一个晶体管到另一个所引入的粒度的物质在这一尺度。格拉斯哥大学电子工程系的器件模拟小组（阿森阿森诺夫）是CMOS可变性模拟的世界领导者，他们开发了独特的计算工具，为促进下一代纳米CMOS的设计而量身定制。虽然这些技术非常适合模拟离散掺杂剂的影响，但它们在模拟线边缘和界面粗糙度时需要大量的网格点，从而带来了不必要的计算成本。如果能够降低计算成本，将极大地有利于CMOS在纳米尺度上的实际应用模拟。来自格拉斯哥大学土木工程系力学与材料组的J.K.已经开发出了有效的数值技术，这些技术通过利用关于解的先验知识丰富数值方案并允许使用低质量的离散化，而不牺牲精度。这个概念验证研究将调查如何novelnumerical技术设计在Bordas'组的背景下的力学问题可以推广到提高精度与计算成本比在纳米级CMOS模拟器。

Vision: The idea of this proof-of-concept research is to investigatehow recent revolutionary advances in computational mechanics can beleveraged to enhance the modelling of nano complementarymetal-oxide-semiconductor (CMOS).The size of the CMOS devices is aggressively being reduced into thedeca-nanometer range (one hundredth of a micron). It isprojected that mass-produced metal-oxide-semiconductor field-effecttransistors (MOSFETs) will reach gate lengths as small as 7 nanometersby 2018 (2003 edition of the International Technology Roadmap forSemiconductors).Modelling and simulation provides deep insight into the operation ofmodern semiconductor devices and circuits, and dramatically reducesthe development costs and time-to-market.Modelling devices at the deca-nanometer scale face significantdifficulties associated with the statistical variability from onetransistor to another introduced by the granularity of matter at thisscale. The Device Modelling Group (Asen Asenov) in the ElectricalEngineering Department at Glasgow University is the world leader inCMOS variability simulation developing unique computational tools tailored tofacilitate the design the next generation of nano-CMOS.While these techniques are very well suited to simulate the effects ofdiscrete dopants, they involve an unnecessary computational cost byrequiring large numbers of grid points when simulating line edge andinterface roughness. It would be greatly beneficial for the practical use simulations of CMOS atthe nano-scale if this computational cost could be reduced.Stephane Bordas, from the Mechanics and Materials Group of the CivilEngineering Department at Glasgow University has developed efficientnumerical techniques which have the potential to significantlydecrease the computational burden through enrichment of the numericalscheme with a priori knowledge about the solution and by allowing theuse of low quality discretisations without sacrificing accuracy.This proof-of-concept research will investigate how the novelnumerical techniques devised in Bordas' group in the context ofmechanics problems can be generalised to increase the accuracy versuscomputational cost ratio in nano-scale CMOS simulators.