Configurable Analogue Transistors: Conquering Unreliability in a Shrinking World

硅基半导体技术的发展正朝着越来越小的组件发展，晶体管被缩小到纳米尺寸。例如，英特尔目前正在开发45纳米和65纳米技术，这些技术将取代目前用于大多数微处理器的90纳米和130纳米工艺。欧洲在这些现代技术方面落后于美国，欧洲在硅基纳米器件电子领域的科学卓越性得到进一步加强是可取的。英国研究人员可以取得重大进展的一个特定领域是研究解决日益低产量问题的办法。随着器件尺寸的缩小，数字电路的性能总体上继续蓬勃发展。在一个芯片上实现多处理器的现实已经实现，65纳米以上的持续成功的前景是光明的。由于这种广泛的集成能力，对AMS支持电路的需求已经增长，主要是数字芯片。在同一片硅片上集成大量的模拟电路功能，为模拟设计带来了新的挑战。因此，系统芯片的模拟部分现在成为一个严重的设计瓶颈。通常，10%的芯片设计在功能上可能是模拟的，但同样的部分可以占用90%的设计时间。现在，模拟设计人员比以往任何时候都更加意识到，他们将像数字设计界一样依赖于设计自动化工具，特别是随着上市时间的压力越来越大，每个芯片设计和工艺节点都无法接受定制模拟设计的智慧。我们提出了一种新颖的方法，可以在制造后改善不良的良率和性能。可配置寻址晶体管（CAT）概念允许在设计中对单个晶体管进行寻址，并调整其宽度。用CAT设备替换模拟功能块中的许多晶体管，可以在制造后实现块的整体特性调整。这允许由于工艺变化而导致的统计性能扩散在硅测试阶段得到补偿，从而导致模具性能的显着改善，从而提高整体产量。所建议的方法之所以优雅，部分原因在于其实现的灵活性。这种灵活性导致了明确的权衡，可以利用它来最大限度地提高特定应用的产量。该方法中有三个主要的权衡点，包括关键设备识别，最佳CAT尺寸和制造后配置。关键器件识别CAT器件比它所取代的晶体管占用更多的面积，因此在增加的面积开销和复杂性之间权衡潜在的好处是很重要的。因此，第一阶段是识别设计中的“关键”晶体管，这些器件的变化最有可能导致设计不符合规范。只有一定数量的关键设备将被CAT设备取代，以确保在开销和产量提高之间取得最佳平衡。优化CAT尺寸和插入在确定将用CAT器件替换哪些晶体管之后，有必要优化这些CAT替代品，以在整体设计方面实现最佳的良率改进。CAT方法应用的一个关键方面将是电子设计自动化（EDA）方法的发展，该方法将管理自动调整尺寸和插入新CAT设备的过程。提出的方法与传统的设计技术有着根本的不同，这个新的研究方向对于解决缩小技术问题所带来的挑战至关重要。

The development of silicon based semiconductor technology is heading towards increasingly smaller components with transistors being scaled down to nanometre dimensions. As an example, Intel are currently developing their 45 nm and 65 nm technologies, which are placed to overtake the current 90 nm and 130 nm processes used for most of their microprocessors. Europe is lagging behind the USA in these modern technologies, and it is desirable that European scientific excellence in the field of silicon based nano-device electronics is further strengthened. A particular area where UK researchers can make significant inroads is to investigate solutions to the problem of increasingly poor yield.As device dimensions shrink, digital circuit performance on the whole continues to thrive. The reality of multi-processors on a single die has been realized and the prospects for continued success beyond 65 nm are bright. Due to this extensive integration capability, the need has grown for AMS support circuitry, on what are predominantly digital chips. Integrating a wide range of analogue circuit functions on the same silicon as vast microprocessor and memory blocks brings about new challenges for analogue design. As a result, the analogue parts of system chips are now becoming a serious design bottleneck. Typically 10% of the chip design may be analogue in function, but this same section can absorb 90% of the design time. Now, more than ever, analogue designers realize they will become as reliant on design automation tools as the digital design community, especially with increasing pressure on time to market precluding the received wisdom of bespoke analogue design for every chip design and process node that emerges. We propose a novel approach that allows poor yield and performance to be improved post manufacture. The Configurable Addressable Transistor (CAT) concept allows an individual transistor within a design to be addressed, and its width adjusted. Replacement of a number of transistors in an analogue functional block with CAT devices allows adjustment of the block's overall characteristics to be achieved after its manufacture. This allows statistical performance spread due to process variations to be compensated for at the silicon test stage, leading to a significant improvement in a die's performance and therefore an improvement in overall yield. The elegance in the proposed approach is partly due to the flexibility of its implementation. This flexibility leads to clear tradeoffs which can be leveraged in order to maximise the improvement in yield for a particular application. There are three main trade-off points in the approach which include critical device identification, optimum CAT sizing and post-manufacture configuration.Critical device identificationA CAT device occupies more area than the transistor it replaces, so it is important to trade-off potential benefits with increased area overheads and complexity. The first stage is therefore to identify 'critical' transistors in the design, where variations in these devices are most likely cause the design to fail specification. Only a certain number of critical devices will be replaced with CAT devices, ensuring the best trade-off between overheads and yield improvement. Optimum CAT sizing and insertionHaving determined which transistors will be replaced with CAT devices, it is necessary to optimise each of these CAT replacements to achieve the best possible yield improvement in terms of the overall design. A key aspect of the application of the CAT approach will be the development of Electronic Design Automation (EDA) methodologies that will manage the process of automatically sizing and inserting the new CAT devicesPost manufacture configurationThe proposed approach is fundamentally different to conventional design techniques and this new research direction is essential to address the challenges emerging from the issue of shrinking technologies.