Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors

由金属-半导体界面组成的接触是任何半导体器件的组成部分。金属和半导体元件的兼容性、其界面的结构和电特性的均匀性以及接触的坚固性和耐久性对于器件的正常功能至关重要。接触的最佳操作是实现新型器件和开发新器件概念的关键，包括基于高迁移率半导体的CMOS、隧道和自旋晶体管、隧道二极管、气体和红外碳纳米管探测器等。半导体工业中的两个主要的当前趋势-器件的小型化和向新材料的转变-对接触技术提出了挑战：（i）在越来越小的器件中操作的鲁棒性和稳定性以及（ii）金属和半导体部件的兼容性。例如，目前接触的电阻受到当前正在开发的亚22纳米技术的波动的强烈影响。对于较小的设备，这个问题越来越严重。另一方面，引入用于高迁移率沟道的新材料，例如，Ge和III-V族，需要寻找兼容的金属，并带来了与接触制造相关的新挑战。因此，理解纳米级金属-半导体界面性质对该界面的原子结构、化学成分无序和缺陷的依赖性是制定和开发新器件概念的关键。本研究的主要目的是：（1）实现和实施金属-半导体界面的最佳化学成分和结构的多尺度模拟，使肖特基势垒最小化; ii）分析界面缺陷，应变，我们将首先发展一种方法，将原子尺度结构的从头计算模拟与1- 10原子界面的电子性质联系起来，3 nm尺度下的器件电流-电压特性的模拟。从头计算的结果将被转移到3D Monte Carlo（MC）输运模拟中，这将使我们能够对金属-半导体界面进行真实的表示，并开发源极/漏极接触的物理模型。该模型，反过来，将被纳入到一个二维MC设备模拟器，以预测设备的性能，从而允许一个直接从操作设备获得的实验数据进行比较。这种方法将使我们能够：i）明确考虑点缺陷的影响（<0.5 nm刻度），成分紊乱（~1 nm规模），金属粒度（~1-2 nm尺度）对所选金属-半导体界面的电子性质的影响，ii）将这些效应结合到通过金属-半导体界面的3D MC输运模拟中，iii）开发用于源极/漏极接触的真实模型，进行2D MC器件模拟，并根据接触特性优化器件性能。该方法将首先在钛金属接触原型III-V族半导体GaAs的情况下进行测试，并使用我们的项目合作伙伴提供的实验数据验证结果。然后将研究其他系统的复杂性增加：界面的Ti金属与一元Si和Ge，掺杂GaAs，和三元InGaAs半导体，最后，界面的TiN金属合金与InGaAs。我们的理论预测将被验证，并在每个规模的实验结果进行比较：透射电子显微镜（TEM）数据的接口结构，电阻测量通过接口的运输，I-V特性的设备模拟。

Contacts, made up of metal-semiconductor interfaces, are integral parts any semiconductor device. Compatibility of the metal and semiconductor components, homogeneity of structural and electrical characteristics of their interfaces, and robustness and durability of the contacts are crucial for the device proper functionality.Optimal operation of the contacts is a key to realisation of novel devices and development of new device concepts, including high mobility semiconductors based CMOS, tunnelling and spin-based transistors, tunnelling diodes, gas and infrared carbon-nanotube detectors, etc. Two major current trends in the semiconductor industry - miniaturisation of the devices and shift to new materials - pose the challenges for the contact technology: (i) robustness and stability of operation in ever smaller devices and (ii) compatibility of metal and semiconductor components. For example, the resistance of present day contacts is strongly affected by fluctuations in the currently being developed sub-22 nm technology. This problem is getting worse for smaller devices. On the other hand, introduction of new materials for high-mobility channels, e.g., Ge and III-Vs, necessitates the search for compatible metals and brings new challenges related to the contact fabrication. Therefore, understanding the dependence of the nanoscale metal-semiconductor interface properties on the atomic structure of this interface, chemical composition disorder, and defects is a key to formulating and exploiting new device concepts. In particular, this understanding is imperative for the developing of optimal contact fabrication procedures for nano-scale semiconductor devices.Primary aims of the proposed research are i) enabling and carrying out multiscale modelling of the optimal chemical compositions and structures of metal-semiconductor interfaces such that the Schottky barrier is minimal;ii) analysis of the role of interface defects, strain, and disorder on the carrier transport in CMOS devices.We will first develop a methodology which bridges ab initio simulations of atomic-scale structures and electronic properties of interfaces at 1-3 nm scale and simulation of device current-voltage characteristics at the scale of 5-50 nm. The results of the ab initio calculations will be transferred into 3D Monte Carlo (MC) transport simulations, which will allow us to make a realistic representation of the metal-semiconductor interface and develop a physical model of source/drain contacts. This model, in turn, will be incorporated into a 2D MC device simulator to predict the device performance and thus allow one for the straightforward comparison with experimental data obtained directly from the operating devices. Such methodology will allow us: i) to consider explicitly effects of point defects (<0.5 nm scale), composition disorder (~1 nm scale), and metal granularity (~1-2 nm scale) on the electronic properties of selected metal-semiconductor interfaces, ii) to incorporate these effects into 3D MC transport simulations through the metal-semiconductor interfaces,iii) to develop realistic models for source/drain contacts, carry out 2D MC device simulations, and to optimise device performance with respect to the properties of the contacts.The methodology will be first tested on the case of Ti metal contact with an archetypal III-V semiconductor GaAs and the results will be validated using experimental data provided by our project partners. Then other systems of increasing complexity will be investigated: interfaces of Ti metal with unary Si and Ge, doped GaAs, and ternary InGaAs semiconductors and, finally, interfaces of TiN metal alloy with InGaAs. Our theoretical predictions will be validated by and compared to experimental results at each scale: Transmission Electron Microscopy (TEM) data for the interface structures, resistance measurements for the transport through the interface, I-V characteristics for the device simulations.