Silicon-based Fault-Tolerant Quantum Computing

量子计算刚刚进入了一个新时代，即噪声中等规模量子（NISQ）技术，在这个技术中，量子处理器能够执行超越世界上最伟大的超级计算机能力的计算。这一非凡的成就为量子计算（QC）树立了一个重要的里程碑，并将重点放在QC路线图的最终目标上：构建一个容错的量子机器。一台拥有足够的无差错计算资源来运行量子算法的机器，它有可能从根本上改变社会。算法将帮助我们更好地预测天气和金融市场，加快对无序数据库的搜索，这对大数据时代至关重要，最重要的是，加速新材料和新药物的发现步伐，这与我们生活的时代息息相关。尽管构成机器的单个量子比特具有固有的噪声性质，但实现容错QC的最有希望的途径将需要量子纠错（QEC）来实现精确计算。这个想法是基于将逻辑信息分布在许多物理量子位上。只要物理量子位满足最大错误率（对于最宽容的方法，表面代码为1%），就可以实现容错。确切的物理量子位开销（每个逻辑量子位）取决于错误率，但考虑到最先进的量子位保真度，它可能会超过100个数字。然后，QEC预计将把所需的物理量子比特数量提高到数千个，用于经济上重要的算法，而对于一些要求更高的量子计算应用，则需要数百万个。因此，缩放是一个普遍的科学和技术挑战。基于硅纳米器件中单个电子的自旋自由度来构建量子比特，与其他竞争技术相比，有许多优势，比如最紧凑的固态方法的可扩展性，以及硅晶体管技术用于制造数十亿元集成电路的广泛工业基础设施。此外，硅电子自旋量子位元是本质上最相干的系统之一，其特性使其能够演示所有操作步骤-初始化，控制和读出-具有足够的容错计算精度。然而，迄今为止取得的大多数成果都来自于在学术洁净室中制造的设备，可重复性相对较低，最多只能在一个或两个量子位处理器中制造[Huang等人]。《自然》[j]。但最近的单孔自旋量子位的演示[Maurand etal . Nat commons 7 13575]以及在300毫米互补金属氧化物半导体（CMOS）平台上制造的设备中的电子自旋控制和读取，为从基于实验室的原理验证实验到大规模制造量子位的过渡提供了机会[Gonzalez-Zalba etal ., Physics World(2019)]。在SiFT项目中，我将基于我在基于cmos的量子计算方面的开创性工作[Nat comm 6 6084， Nat Elect 2 236, Nat Nano 14 437]，首次演示运行表面代码的所有必要步骤。我将以二维量子比特晶格为目标，在那里可以检测和纠正任意量子错误，使量子比特集群比单个组成部分更可靠。我的量子电路设计将在实验和商业硅铸造厂制造，使用非常大规模的集成工艺。该项目将成为在英国建造大型硅基量子处理器的垫脚石，该处理器具有足够的无差错计算资源，可以对社会产生影响。它将帮助QC超越NISQ进入容错时代，在这个时代，QC的计算承诺可以得到充分利用。

Quantum computation has just entered a new era, that of Noisy Intermediate-Scale Quantum (NISQ) technologies in which quantum processors are able to perform calculations beyond the capabilities of the world's greatest supercomputers. This remarkable achievement sets an important milestone in quantum computing (QC) and brings focus towards the ultimate goal of the QC roadmap: building a fault-tolerant quantum machine. A machine with sufficient error-free computing resources to run quantum algorithms with the potential to radically transform society. Algorithms that will help us better forecast weather and financial markets, speed up searches in unsorted databases, essential for the Big Data era, and most importantly, accelerate the pace of discovery of new materials and medicines, so relevant for the times we live in. The most promising routes to fault-tolerant QC will require quantum error correction (QEC) to enable accurate computing despite the intrinsically noisy nature of the individual quantum bits constituting the machine. The idea is based on distributing the logical information over a number of physical qubits. As long as the physical qubits satisfy a maximum error rate (1% for the most forgiving method, the surface code) fault-tolerance can be achieved. The exact physical qubit overhead (per logical qubit) depends on the error rate but considering state-of-the-art qubit fidelities, it will likely be a figure in excess of a hundred. QEC is then expected to take the number of required physical qubits to many thousands for economically significant algorithms and to many millions for some of the more demanding quantum computing applications. Scaling is hence a generic scientific and technological challenge.Building qubits based on the spin degree of freedom of individual electrons in silicon nanodevices offers numerous advantages over competing technologies such as the scalability of the most compact solid-state approach and the extensive industrial infrastructure of silicon transistor technology devoted to fabricating multi-billion-element integrated circuits. Besides, silicon electron spin qubits are one of the most coherent systems in nature, characteristic that has enabled demonstrating all the operational steps - initialization, control and readout - with sufficient level of precision for fault-tolerant computing. However, most of the results achieved so far come from devices fabricated in academic cleanrooms with relatively low level of reproducibility and in one- or two-qubit processors at best [Huang et al. Nature 569, 532]. But the recent demonstration of a single hole spin qubit [Maurand et al Nat Commun 7 13575] and electron spin control and readout in devices fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) platform open an opportunity to trigger a transition from lab-based proof-of-principle experiments to manufacturing qubits at scale [Gonzalez-Zalba et al, Physics World (2019)]. In the project SiFT, I will build on my pioneering work on CMOS-based quantum computing [Nat Commun 6 6084, Nat Elect 2 236, Nat Nano 14 437] to demonstrate, for the first time, all the necessary steps to run the surface code. I will target a two-dimensional qubit lattices where arbitrary quantum errors could be detected and corrected making clusters of qubits more reliable that the individual constituents. My quantum circuit designs will be manufactured in experimental and commercial silicon foundries that use very large-scale integration processes. The project will be the steppingstone towards building in the UK a large-scale silicon-based quantum processor with sufficient error-free computational resources to make an impact on society. It will help take QC beyond NISQ into the fault-tolerant era where the computational promises of QC can be fully exploited.