NANOSECOND RADIOFREQUENCY SWITCH DRIVER DESIGN UPGRADE & HYBRIDIZATION

这个子项目是许多研究子项目中利用 资源由NIH/NCRR资助的中心拨款提供。子项目和 调查员(PI)可能从NIH的另一个来源获得了主要资金， 并因此可以在其他清晰的条目中表示。列出的机构是 该中心不一定是调查人员的机构。 改进的射频快速切换(R.F.)在Acert下一代脉冲ESR光谱仪的设计中，通过PIN二极管开关提供能量对于接收器保护和减少死区时间至关重要。用于PIN开关的新型专用电子驱动器的制造以前已在Freed Research Group内完成(美国专利#5,214,315)。本发明的一个独特特征是，它在典型的Si和GaAsPIN二极管阵列的反应加载条件下优化了转变速度。我们目前正在通过建模和指定更高性能的功率MOSFET半导体并将开关驱动器重新格式化为高性能混合电路来升级驱动器。通过最小化与电路互连相关的寄生电感，将包括开关驱动器的分立组件集成到紧凑的陶瓷基板上将显著提高开关速度。我们采用先进的商业软件工具，以便准确地模拟高阶互连寄生和半导体特性；这一功能允许高效模拟和选择最适合此应用的较新半导体。它还可以准确预测微小寄生电抗的大小和影响，大大减少布局变化收敛所需的时间。 模拟研究表明，对于15-20 NC的电荷转移，最新的混合驱动器设计应该在6-8 ns的水平上执行。这个数字转化为可能的R.F.大功率硅PIN二极管阵列的开关速度为10-14 ns，高压为4-6 ns。砷化镓PIN阵列。驱动器混合组件在物理上很小，因此可以非常接近其关联的PIN阵列，从而最大限度地减少有害的传输线效应和电磁干扰。我们正在评估更多的候选PIN器件，并计划在我们正在进行的微波光谱仪开发的背景下对PIN二极管进行表征后，要求使用混合驱动器。

This subproject is one of many research subprojects utilizing the resources provided by a Center grant funded by NIH/NCRR. The subproject and investigator (PI) may have received primary funding from another NIH source, and thus could be represented in other CRISP entries. The institution listed is for the Center, which is not necessarily the institution for the investigator. Improved fast switching of radiofrequency (r.f.) energy via PIN-diode switches is essential for receiver protection and deadtime reduction in the design of ACERT next-generation pulsed-ESR spectrometers. Fabrication of a novel, specialized electronic driver for PIN switches has previously been accomplished within the Freed Research Group (U.S. patent #5,214,315). A unique feature of this invention is that it optimizes transition speed under reactive loading conditions typical of Si and GaAs PIN-diode arrays. We are currently upgrading the driver by modeling and specifying higher-performance power MOSFET semiconductors and reformatting the switch driver as a high-performance hybrid circuit. Integration of the discrete components comprising the switch driver onto a compact ceramic substrate will significantly improve switching speed by minimizing parasitic inductance associated with the circuit interconnects. We are employing advanced commercial software tools in order to accurately model the higher-order interconnect parasitics and semiconductor characteristics; this capability allows efficient simulation and selection of newer semiconductors best-suited to this application. It also permits accurately predicting the magnitude and effect of minute parasitic reactances, greatly reducing the time required for convergence of layout variations. Simulation studies indicate that the most recent hybrid driver design should perform at the 6 - 8 ns level for charge transfers of 15-20 nC. This figure translates to probable r.f. switching speeds in the 10 - 14 ns range for high-power silicon PIN diode arrays, or 4 - 6 ns for h.v. GaAs PIN arrays. The driver hybrid assembly is physically small and can therefore be situated in close proximity to its associated PIN arrays, minimizing detrimental transmission-line effects and electromagnetic interference. We are evaluating further candidate PIN devices and plan to requisiton the hybrid drivers once the PIN diodes have been characterized in the context of our ongoing microwave spectrometer development.