Visualization systems for FPGA architectures and CAD algorithms

对于希望开发基于硬件的产品的加拿大中小型公司来说，1000万美元以上的巨额非经常性工程(NRE)费用是一个重要的进入壁垒。这些障碍被现场可编程门阵列(现场可编程门阵列)打破，现场可编程门阵列是一种通用微芯片。一个FPGA可以被配置成实现任何数字电路，而不需要昂贵的芯片制造厂。然而，这种灵活性导致了限制容量、速度和功率的开销。但是，通过使用低至22 nm的先进集成电路技术来构建FPGA，可以极大地降低这种开销。虽然目前的工业现场可编程门阵列的研究和开发主要集中在基于65 nm技术的下一代可用半导体工艺上，但学术研究应该着眼于更远的未来，即45 nm到22 nm技术。根据2005年国际半导体技术路线图(ITRS)，这些技术将在2010和2016年，或从现在起4年和10年后推出。在这项研究中，我们正在为未来的现场可编程门阵列研究新的体系结构和算法。新一代现场可编程门阵列将拥有比目前的现场可编程门阵列更高的逻辑容量和更高的时钟速度，从而支持许多新的新兴应用。它们还将需要显著不同的体系结构和更快的相关计算机辅助设计算法，因为目前的方法不能很好地扩展。目前商用的65 nm CAD工具需要数小时或数天才能找到布线解决方案；在22 nm的情况下，这是不可接受的，因为在这里，现场可编程门阵列大约要大10倍。此外，解决互连布线问题需要大量内存，因为每条线路和每个开关(即，每个多路复用器输入)都需要在整个算法中保持重要的状态信息。在22 nm半导体技术节点上，需要具有大存储容量的可视化工作站来开展对FPGA体系结构和CAD算法的研究。

Large non-recurring engineering (NRE) fees of $10 million+ are a significant barrier to entry for small and mid-sized Canadian companies that hope to develop hardware-based products. These barriers are shattered by Field-Programmable Gate Arrays (FPGAs), a type of universal microchip. An FPGA can be configured to implement any digital circuit, without the need for an expensive chip-fabrication plant.  This flexibility, however, results in overhead that limits capacity, speed, and power.  This overhead is dramatically reduced by building FPGAs with advanced integrated circuit technology down to 22nm. While current industrial FPGA research and development is heavily focused on the next-available semiconductor process based on 65nm technology, academic research should be looking further ahead, namely at 45nm to 22nm technologies.  According to the 2005 International Technology Roadmap for Semiconductors (ITRS), these will be available in 2010 and 2016, or 4 and 10 years from now. In this research, we are investigating new architectures and algorithms for future FPGAs. Next-generation FPGAs will have much higher logic capacity and run at higher clock speeds than current FPGAs, enabling many new emerging applications. They will also require significantly different architectures and faster associated Computer-Aided Design algorithms because current approaches do not scale well. Current commercial 65nm CAD tools take hours or days to find a routing solution; this is unacceptable at 22nm where FPGAs will be roughly 10x larger. In addition, solving the interconnect routing problem requires a huge amount of memory because every wire and every switch (i.e., every multiplexer input) needs to keep significant state information throughout the algorithm. Visualization workstations with large memory capacity are required to pursue research into FPGA architecture and CAD algorithms at the 22nm semiconductor technology node.