Design and VLSI implementations of DSP algorithms for communication systems

拟议的研究将在通信系统的数字信号处理(DSP)算法的设计和VLSI实现中利用创新解决方案的探索。将采用高性能、低复杂性和低功耗的解决方案。该项目的目标是：(1)进一步开发具有较短收敛时间(TTC)质量的盲均衡技术，以适应高速通信系统以及无线通信标准(即DPSK、DQPSK、GMSK等)中实施的其他调制方案。(2)进一步发展计算效率高的盲自适应均衡技术，既减少计算量，从而增加系统吞吐量，和/或降低硬件复杂度。(3)开发可编程/可重构的盲自适应均衡器，使其滤波长度、自适应参数和误差度量根据多标准未来通信设备(也如软件定义的无线电)接收机中使用的调制而可变。(4)开发低硬件复杂度和/或计算效率的自适应算法，用于通信系统中的回波抵消应用。(5)在盲自适应均衡器和自适应回声消除器(AECs)中实现低功耗，以响应快速增长的移动通信服务的日益增长的需求。(6)开发同时满足高速、低功耗和低复杂度要求的盲自适应均衡器和回声抵消器的VLSI实现。(7)实现802.11a/RA在高车速下的性能增强和健壮性，以便在5.9 GHz专用短程通信(DSRC)系统中实现更高的数据速率。(8)确认可行性，考虑接收机设计的复杂性，并保持与802.11a/RA标准的一致性。

The proposed research will leverage the invistigation of innovative solutions in the design and VLSI implementations of digital signal processing (DSP) algorithms for communication systems. Solutions that would lead to high performance, low complexity and low-power consumptions will be adopted. Objectives of the project are: (1) To further develop blind equalization techniques that have shorter time-to-convergence (TTC) quality to suit high-speed communication systems and for other  modulation schemes implemented in wireless communication standards (i.e., DPSK, DQPSK, GMSK, etc.). (2) To further develop computationally-efficient blind adaptive equalization techniques that reduce both the amount of computations and hence increase the system's throughput, and/or decrease hardware complexity. (3)To develop programmable/reconfigurable blind adaptive equalizer so that their filter lengths, adaptation parameters, and error measure are variables according to the modulation utilized in the receiver for multi-standard future communication equipments (also as in software-defined radios). (4) To develop low-lardware-complexity and/or computationally-efficient adaptive algorithms for echo cancellation applications in communication systems. (5)To achieve low-power in blind adaptive equalizers and adaptive echo cancellers (AECs) to respond to the increased demand of fast-growing mobile communication services. (6)To develop VLSI implementations of blind adaptive equalizers and echo cancellers that incorporate both high-speed, low-power, and low-complexity requirements. (7) To achieve performance enhancement and robustness of 802.11a/RA for high vehicular velocity, so that higher data rates may be achieved in a 5.9GHz Dedicated Short Range Communication (DSRC) system.   (8)To confirm feasibility, consider the complexity of the receiver design, and maintain consistency with the 802.11a/RA standard.