Low-voltage and low-power mixed-signal ICs in deep-submicron CMOS technology

主要出于经济原因，模拟集成电路(IC)设计者被迫使用占主导地位的数字CMOS技术来开发电路。在CMOS中，电源电压继续降低到1V以下。即使工艺技术不需要降低电源电压，但对电池供电的微系统(如便携式消费电子产品、计算设备、无线通信系统和生物医学植入物)的依赖迅速增长，导致对在低电源电压下工作、低功耗和能够高频工作的高性能IC的需求增加。除了对性能改进的持续推动之外，还有摩尔定律的持续推进，该定律推动了微系统在纳米CMOS工艺中的实现。由于固有的小信号增益和器件余量的减小，高性能模拟电路在纳米级CMOS中的实现变得越来越困难，使得以前可以接受的模拟拓扑和技术变得过时。因此，需要新的专业设计技术、新的拓扑结构和新的体系结构。这为本研究项目的开展提供了动力。它探索了低电压和低功耗模拟IC的设计技术，并为未来微系统的实现开发了新的高性能模拟器件。

Analog integrated circuits (IC's) designers have been forced, primarily by economics, to develop circuits using the dominant digital CMOS technologies. In CMOS the supply voltage continues to scale down below 1 V. Even if the process technology didn't require reduced supply voltages, the rapidly growing reliance on battery-powered microsystems (such as portable consumer electronics, computing devices, wireless communication systems, and biomedical implants) has led to an increase need for high performance ICs that operate under low supply voltage, consume low-power and capable of high frequency operation. On top of this continuous drive for performance improvement, there is also the continuing march of Moor's Law, which drives microsystems to be implemented in nanometer CMOS process. High performance analog circuits become increasingly difficult to implement in nano-scale CMOS due to the reduced intrinsic small signal gain and device headroom, making previously acceptable analog topologies and technologies become obsolete. Therefore, new specialized design techniques, new topologies and new architectures are needed. This provides the motivation for this research project. It explores low-voltage and low-power analog IC's design techniques and develops new high performance analog devices for future microsystems implementation.