Multi-core embedded systems: computer aided NoC/MPSoC design and simulation techniques

嵌入式计算机是支持系统整体功能的更大系统的一部分。嵌入式应用范围从复杂的飞机飞行控制到消费产品。在嵌入式系统的设计中，结合硬件/软件协同综合过程是生产最佳嵌入式设备的关键。本文研究了多处理器片上系统和多核嵌入式系统的协同综合设计方法。MPSoC的性能取决于片上通信网络能否满足处理器与其他核之间的通信需求。据称，基于NoC（片上网络）的系统对于几种产品变体在经济上是可行的。我们调查各种方法的设计和分析的NoC系统。我们建议开发的方法来设计最佳的NoC系统，考虑芯片布局，功率，线长和其他信息。 基于禁忌搜索的方法将采用自动设计技术生成NoC拓扑，结合平面图信息，以获得包括路由器和链路在内的NoC组件的功耗的准确值。还将应用会合交互竞争分析方法，该方法使用分层网络竞争模型来观察NoC组件之间的异步交互，并在NoC合成期间识别可能的竞争点。 为了帮助复杂的片上系统的设计过程中，我们也正在探索使用SystemC语言的NoC仿真环境。内部开发的NoC仿真环境正在通过包括片上组件的功率和芯片布局信息来增强。本研究的动机是需要自动化的多核高性能单芯片嵌入式设备的设计过程。特别受益的嵌入式应用包括航空航天、医疗仪器、多媒体和电信系统。

An embedded computer is part of a larger system that supports overall functioning of the system. Embedded applications range from sophisticated aircraft flight control to consumer products. The incorporation of hardware/software co-synthesis process in the design of embedded systems is crucial for producing optimal embedded devices. We investigate co-synthesis approaches to design MPSoCs (Multi-Processor Systems-on-Chip) and multi-core embedded systems. MPSoC performance is determined by the ability of on-chip communication network that can fulfill the communication needs of processors and other cores. It is claimed that NoC (Network-on-Chip) based systems are economically feasible for several product variants. We investigate various approaches to the design and analysis of NoC systems. We propose to develop methods to design optimal NoC systems by considering chip layout, power, wire-lenths and other information. A Tabu search based approach will be employed for NoC topology generation with an automated design technique, incorporating floor-plan information to attain accurate values of power consumption of NoC components including routers and links. A rendezvous interaction contention analysis method will also be applied that uses a Layered Queuing Network contention model to observe asynchronous interactions amongst the NoC components and identify possible contention points during NoC synthesis. To aid the design process of complex systems-on-chip, we are also exploring NoC simulation environments using SystemC language. An in-house developed NoC simulation environment is being enhanced by including on-chip components' power and chip layout information. This research is motivated by the need to automate the design process for multi-core high performance single chip embedded devices. Embedded applications that would particularly benefit include aerospace, medical instrumentation, multimedia and telecom systems.