Design of multi-core embedded systems using transaction level models

使用事务级模型设计多核嵌入式系统

• 批准号: 386311-2010
• 负责人: Abdi, Samar
• 金额: $ 2.33万
• 依托单位: Concordia University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2012
• 资助国家: 加拿大
• 起止时间: 2012-01-01 至 2013-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=508317
• 关键词: Design; multi; core; embedded; systems

The limitations of process technology and the performance/power requirements of modern applications will continue to drive the adoption of multi-core embedded systems in the foreseeable future. However, application complexity, design cost and short time-to-market pose significant challenges to the design of multi-core embedded systems. Transaction Level Models (TLMs) are emerging as the next higher level of design abstraction above conventional Cycle-Accurate Models for system validation. However, in order to use TLMs for design, novel TLM-based design methods must be developed.

在可预见的未来，工艺技术的局限性和现代应用的性能/功耗要求将继续推动多核嵌入式系统的采用。然而，应用复杂性、设计成本和上市时间短对多核嵌入式系统的设计提出了重大挑战。事务级模型（tlm）作为下一个更高层次的设计抽象出现在传统的周期精确模型之上，用于系统验证。然而，为了使用tlm进行设计，必须开发新的基于tlm的设计方法。