Bridging the Programmability Gap of Compute Accelerators

在过去的几年里，人们对计算加速器的兴趣与日俱增。计算加速器是一种大规模并行设备，具有以低功耗提供高性能的潜力。这种日益增长的兴趣是由智能手机和平板电脑的激增推动的，用户需要更多的功能和更长的电池寿命。它还受到在许多领域解决计算密集型问题的持续需求的推动，如大数据处理、计算金融、环境建模、生物信息学和物理设计。本研究集中于两种类型的计算加速器：图形处理单元(GPU)和现场可编程门阵列(FPGA)。 阻碍计算机加速器广泛使用的一个主要障碍是，软件开发人员发现它们很难编程。GPU要求开发人员探索大量程序优化，这些优化对性能和功率的综合影响很难预测。开发人员经常求助于对可能的优化组合进行广泛的探索--这是一个乏味且容易出错的过程。同样，现场可编程门阵列需要硬件设计专业知识，而且开发周期很长，这使得大多数软件开发人员无法接触到它们。这些障碍得到了科学界的认可，并被统称为加速器的可编程性差距。它们被确定为当今这些平台面临的最突出问题。 这项提案中研究的目标是通过软件创新，特别是编译器和运行时支持，弥合这一可编程性差距。我们的工作将有两个主要推动力。首先，我们将研究和构建一个基于编译器的框架，用于自动调整GPU应用程序，即高效地在可能的优化空间中进行搜索，并选择最有利于性能和/或功率的组合。我们将为这种搜索开发新的启发式算法，并将它们集成到我们的GPU编译器基础设施中来构建框架。在第二个推力中，我们将探索和开发新的方法，使软件开发人员能够在没有硬件设计专业知识的情况下使用现场可编程门阵列，并以快速的方式做到这一点。我们将采用一种方法，使我们开发的能够为应用定制并通过即时编译透明地使用的FPGA覆盖--一种本身可配置的FPGA电路。 实现我们建议的研究目标将使更多的软件开发人员能够使用计算加速器。这将允许开发人员构建性能更好的应用程序，在移动设备上消耗更少的能源。它还将使科学家和工程师能够更好地利用这些新兴平台更快地解决他们的问题，使他们能够在各自的领域取得进展。

The past few years have seen increasing interest in compute accelerators—massively parallel devices that have the potential to deliver high performance at low power. This increasing interest is driven by the proliferation of smart phones and tablets, where users demand more functionality and longer battery life. It is also driven by the continual need to solve computationally intensive problems in many domains, such as big data processing, computational finance, environmental modeling, bioinformatics and physical design. This research focuses on two types of compute accelerators: Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). A main hurdle preventing the wide spread use of compute accelerators is that software developers find them difficult to program. GPUs require developers to explore a host of program optimizations whose combined impact on performance and power is hard to predict. Developers often resort to an extensive exploration of possible combinations of the optimizations—a tedious and error prone process. Similarly, FPGAs demand hardware design expertise and have lengthy development cycles, which make them inaccessible to most software developers. These hurdles recognized by the scientific community and have been collectively referred to as the programmability gap of accelerators. They have been identified as the most outstanding problem facing these platforms today. The goal of the research in this proposal is to bridge this programmability gap through innovations in software, particularly in compilers and run-time support. Our work will have two main thrusts. In the first, we will investigate and build a compiler-based framework for automatically tuning GPU applications, i.e., for efficiently searching through the space of possible optimizations and selecting a combination that is best for performance and/or power. We will develop novel heuristics for this search and integrate them into our GPU compiler infrastructure to build the framework. In the second thrust we will explore and develop novel approaches to make it possible for software developers to use FPGAs without hardware design expertise and do so in a speedy manner. We will pursue an approach that enables an FPGA overlay—an FPGA circuit that is in itself configurable—that we developed to be customized for applications and to be transparently used through just-in-time compilation. Achieving the goals of our proposed research will enable the use of compute accelerators by more software developers. This will allow developers to build better performing applications that consume less energy on mobile devices. It will also enable scientists and engineers to better utilize these emerging platforms to solve their problems faster, enabling advances in their respective domains.