Bridging the Programmability Gap of Compute Accelerators

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The past few years have seen increasing interest in compute accelerators-massively parallel devices that have the potential to deliver high performance at low power. This increasing interest is driven by the proliferation of smart phones and tablets, where users demand more functionality and longer battery life. It is also driven by the continual need to solve computationally intensive problems in many domains, such as big data processing, computational finance, environmental modeling, bioinformatics and physical design. This research focuses on two types of compute accelerators: Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs).***A main hurdle preventing the wide spread use of compute accelerators is that software developers find them difficult to program. GPUs require developers to explore a host of program optimizations whose combined impact on performance and power is hard to predict. Developers often resort to an extensive exploration of possible combinations of the optimizations-a tedious and error prone process. Similarly, FPGAs demand hardware design expertise and have lengthy development cycles, which make them inaccessible to most software developers. These hurdles recognized by the scientific community and have been collectively referred to as the programmability gap of accelerators. They have been identified as the most outstanding problem facing these platforms today.***The goal of the research in this proposal is to bridge this programmability gap through innovations in software, particularly in compilers and run-time support. Our work will have two main thrusts. In the first, we will investigate and build a compiler-based framework for automatically tuning GPU applications, i.e., for efficiently searching through the space of possible optimizations and selecting a combination that is best for performance and/or power. We will develop novel heuristics for this search and integrate them into our GPU compiler infrastructure to build the framework. In the second thrust we will explore and develop novel approaches to make it possible for software developers to use FPGAs without hardware design expertise and do so in a speedy manner. We will pursue an approach that enables an FPGA overlay-an FPGA circuit that is in itself configurable-that we developed to be customized for applications and to be transparently used through just-in-time compilation.***Achieving the goals of our proposed research will enable the use of compute accelerators by more software developers. This will allow developers to build better performing applications that consume less energy on mobile devices. It will also enable scientists and engineers to better utilize these emerging platforms to solve their problems faster, enabling advances in their respective domains.**