Bridging the Programmability Gap of Compute Accelerators

在过去的几年里，人们对计算加速器的兴趣越来越大，这种大规模并行设备有可能以低功耗提供高性能。这种日益增长的兴趣是由智能手机和平板电脑的激增驱动的，用户需要更多的功能和更长的电池寿命。这也是由于在许多领域不断需要解决计算密集型问题，如大数据处理，计算金融，环境建模，生物信息学和物理设计。本研究重点关注两种类型的计算加速器：图形处理单元（GPU）和现场可编程门阵列（FPGA）。阻止计算加速器广泛使用的一个主要障碍是软件开发人员发现它们很难编程。GPU要求开发人员探索大量程序优化，这些优化对性能和功耗的综合影响难以预测。开发人员经常求助于对可能的优化组合进行广泛的探索-这是一个乏味且容易出错的过程。同样，FPGA需要硬件设计专业知识，并且开发周期很长，这使得大多数软件开发人员无法使用。这些障碍被科学界所认识，并被统称为加速器的可编程性差距。这些问题已被确定为这些平台目前面临的最突出问题。*本提案中研究的目标是通过软件创新，特别是编译器和运行时支持，弥合这一可编程性差距。我们的工作将有两个主要目标。首先，我们将研究并构建一个基于编译器的框架，用于自动调整GPU应用程序，即，用于有效地搜索可能的优化空间并选择对于性能和/或功率最佳的组合。我们将为此搜索开发新的算法，并将其集成到我们的GPU编译器基础设施中，以构建框架。在第二个重点中，我们将探索和开发新的方法，使软件开发人员能够在没有硬件设计专业知识的情况下使用FPGA，并以快速的方式完成。我们将寻求一种方法，使FPGA覆盖-一个本身可配置的FPGA电路-我们开发的是定制的应用程序，并通过即时编译透明地使用。实现我们提出的研究目标将使更多的软件开发人员能够使用计算加速器。这将使开发人员能够构建性能更好的应用程序，在移动的设备上消耗更少的能源。它还将使科学家和工程师能够更好地利用这些新兴平台来更快地解决他们的问题，从而在各自的领域取得进步。

The past few years have seen increasing interest in compute accelerators-massively parallel devices that have the potential to deliver high performance at low power. This increasing interest is driven by the proliferation of smart phones and tablets, where users demand more functionality and longer battery life. It is also driven by the continual need to solve computationally intensive problems in many domains, such as big data processing, computational finance, environmental modeling, bioinformatics and physical design. This research focuses on two types of compute accelerators: Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs).***A main hurdle preventing the wide spread use of compute accelerators is that software developers find them difficult to program. GPUs require developers to explore a host of program optimizations whose combined impact on performance and power is hard to predict. Developers often resort to an extensive exploration of possible combinations of the optimizations-a tedious and error prone process. Similarly, FPGAs demand hardware design expertise and have lengthy development cycles, which make them inaccessible to most software developers. These hurdles recognized by the scientific community and have been collectively referred to as the programmability gap of accelerators. They have been identified as the most outstanding problem facing these platforms today.***The goal of the research in this proposal is to bridge this programmability gap through innovations in software, particularly in compilers and run-time support. Our work will have two main thrusts. In the first, we will investigate and build a compiler-based framework for automatically tuning GPU applications, i.e., for efficiently searching through the space of possible optimizations and selecting a combination that is best for performance and/or power. We will develop novel heuristics for this search and integrate them into our GPU compiler infrastructure to build the framework. In the second thrust we will explore and develop novel approaches to make it possible for software developers to use FPGAs without hardware design expertise and do so in a speedy manner. We will pursue an approach that enables an FPGA overlay-an FPGA circuit that is in itself configurable-that we developed to be customized for applications and to be transparently used through just-in-time compilation.***Achieving the goals of our proposed research will enable the use of compute accelerators by more software developers. This will allow developers to build better performing applications that consume less energy on mobile devices. It will also enable scientists and engineers to better utilize these emerging platforms to solve their problems faster, enabling advances in their respective domains.**