Reconfigurable Accelerators for Emerging Machine Learning Workloads

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The availability of high-performance energy-efficient computing is essential in many fields of science and engineering. This is particularly the case for the field of Machine Learning (ML). Such computing has been a propeller for the many innovations this field has brought over the past few years, particularly in the processing of visual data (e.g., facial recognition). High-performance energy-efficient computing is often delivered by accelerator-based systems that combine a general-purpose processor with a custom accelerator, such as a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), or a Neural Processing Unit (NPU). This research focuses on the design and effective use of next-generation accelerators for machine learning. Today, ML accelerators focus on improving the performance of dense matrix computations, ubiquitously found in Convolutional Neural Network (CNN) ML models. However, there are emerging ML models that utilize computations that are not in the form of dense matrix calculations. Examples include Graph Convolutional Neural Networks (GCNNs) that learn from data which represents entities and relationships among them (e.g., users on social media and their interactions or research publications and their citations), embeddings used natural language processing models, and object identification models used in autonomous vehicles. These emerging ML workloads demand new accelerator designs. Thus, the goal of this research is to stay "ahead-of-the curve" and explore a novel accelerator design and its software support for these emerging ML workloads. The research has a number of interrelated themes. One theme is to explore the architecture of a reconfigurable accelerator for the above emerging workloads. The reconfiguration allows an accelerator to be tailored to the ML workload at hand and this, more efficient. A second theme is to explore the tools that are needed to run these workloads on the accelerator, in particular ones for mapping of the workloads to the units of the accelerator. A third theme is the design new compiler optimizations that improve the quality of code on the target accelerator. Successful completion of the proposed research will contribute to knowledge in the areas of ML accelerator design and compiler optimizations. Further, the accelerators and compiler support developed by the work can be used by researchers who explore emerging ML models, enabling fast exploration of GCNNs and thus indirectly contributing to advances in this field. The research will train both graduate and undergraduate students in the intersection of three areas of computer science: accelerator architecture, machine learning and system software. Personnel with such combined expertise are in high demand today.