Circuits and Architecture Innovations for Beyond CMOS Scaling

超越CMOS缩放的电路和架构创新：在过去的几十年里，晶体管栅极长度已经从几微米缩小到几纳米，使今天的近一百万个晶体管占据了几十年前单个晶体管的相同面积。晶体管尺寸的大幅缩小使单个芯片上集成了超过10亿个晶体管，并推动了我们今天所享受的计算性能和数据通信速度。然而，当我们接近栅极长度的原子距离时，晶体管尺寸的进一步缩放变得极其困难。事实上，预计这种缩放将在下两代CMOS技术中结束，栅极长度约为2nm。这种扩展的结束意味着我们不能再增加每个微芯片的晶体管数量，也不能期望计算和通信的指数增长。然而，我们对进一步提高速度的愿望和需要还远远没有结束。事实上，我们这个时代的许多挑战性问题，如环境、健康和金融问题，都需要比CMOS缩放结束时更高的计算速度。该研究计划将使用先进的CMOS技术，在系统和架构层面上进一步提高电子产品的性能。在系统级，我们设计接口电路，将几个芯片“缝合”在一起，有效地增加了每个芯片的晶体管数量。这些电路必须具有小面积和低功率开销，以便将大部分面积和功率留给较大芯片的主要操作。这项研究的预期结果是线性增加的晶体管的数量超过CMOS缩放。架构层面的创新将带来远远超出CMOS规模的巨大好处。在这项研究中，我们将使用已知的模拟退火算法进行优化，目前在软件中实现，并在CMOS中实现它们。考虑到CMOS中可用的大量并行性，我们预计至少有3-4个数量级的加速来解决优化问题。这种水平的加速有望颠覆当前的软件方法，并为解决以前从未解决过的问题铺平道路。这两个研究方向将能够在CMOS缩放结束之后提供性能改进，为量子计算提供桥梁。

Circuits and Architecture Innovations for Beyond CMOS Scaling: Over the past few decades, transistor gate length has shrunk from a few micrometers to a few nanometers, allowing nearly a million transistors today to occupy the same area as a single transistor from a few decades ago. This dramatic shrinkage in transistor size has enabled the integration of over a billion transistors on a single chip, and has propelled both the computation performance and the data communication speed that we enjoy today. However, as we approach the atomic distance in gate length, further scaling of transistor sizes has become exceedingly difficult. In fact, it is expected for this scaling to end in the next two generations of CMOS technology at around 2nm gate length. The end to this scaling means we can no longer increase the number of transistors per microchip, nor can we expect an exponential increase in computations and communications. Yet, our desire and need for further increases in speed are far from over. Indeed, many of the challenging problems of our time, such as those in the environment, health, and finance, require much higher computation speed than what will be available at the end of CMOS scaling. This research program will use advanced CMOS technologies to provide further performance improvements in electronics at the system and the architecture levels. At the system level, we design interface circuits to "stitch" several dies together, effectively increasing the number of transistors per chip. These circuits must have a small area and low power overhead so as to leave most of the area and power for the main operation of the larger chip. The expected outcome of this research is a linear increase in the number of transistors beyond the CMOS scaling. Innovations at the architecture level will provide drastic benefits far beyond the end of CMOS scaling. In this research, we will use known algorithms in simulated annealing for optimization, currently implemented in software, and implement them in CMOS. Given the massive parallelism that is available in CMOS, we expect a speedup of at least 3-4 orders of magnitude for solving optimization problems. This level of speedup is expected to disrupt the current software approach and pave the way for solving problems that have never been solved before. These two research directions will be able to provide performance improvements beyond the end of CMOS scaling, providing a bridge to quantum computing.