Predictable Multicore System-on-Chips for Automotive Safety-critical Systems

汽车在我们的生活中起着至关重要的作用。它们为数百万人提供了最常见的交通方式之一。今天的汽车是机械和计算组件的混合，其中计算组件提供诸如高级驾驶员辅助系统和信息娱乐等功能。多年来，车辆中的计算组件数量不断增加，预计这一趋势将随着全自动驾驶车辆的出现而继续加速。机动车辆的安全性至关重要，因为执行失败可能导致重大伤害或生命损失。因此，应用程序的执行必须在功能上正确，并保证暂时在应用程序建立的范围内。例如，制动延迟可能会造成灾难性后果。这使得汽车成为安全关键系统的一个例子。设计汽车的一个核心原则是确保它们经过认证。例如，ISO-26262是汽车安全关键系统（ASCS）的标准。认证包括确保功能正确的过程，以及应用程序的时间行为在预定期限内的过程。保证执行不会超过最后期限是极具挑战性的。这是因为底层计算组件缺乏时间可预测性。也就是说，很难确定在最坏的情况下应用程序将花费多长时间来执行。这种困难归因于计算组件的设计及其集成以形成片上系统（SoC）。例如，ASCS中的当前SoC是复杂的，具有多核、共享存储器和定制硬件。它们缺乏时间上的可预测性，这并不奇怪。尽管如此，这样的SoC是非常令人垂涎的，因为它们显着降低成本，提高性能，并且节能。我的研究计划的首要目标是为ASCS设计可预测的高性能异构多核SoC。该方案有五个研究目标：（1）研究可预测的高速缓存一致性机制与实用的存储器层次结构和可扩展的基于目录的协议;（2）设计跨异构计算元素的可预测的和一致的数据通信机制;（3）开发编程语言扩展来注释数据共享的属性，用于最坏情况分析;（4）开发可预测的ASCS虚拟化;（5）开发基于可预测的ASCS虚拟化。（5）实现原型系统。这项研究的结果将对加拿大经济和社会产生长期影响。不同规模的行业将能够评估所提出的技术，并有可能将其应用到自己的产品中。结果可能会催生创新产业，例如，可能专注于提供定制解决方案，如专门设计用于支持可预测多核SoC的实时操作系统。

Automotive vehicles play a vital role in our lives. They provide one of the most common modes of transportation for millions of people. Today's automotive vehicles are a mix of mechanical and computing components where the computing components provide features such as advanced driver assistance systems and infotainment. Over the years, the number of computing components in a vehicle has grown and this trend is expected to continue accelerating with fully autonomous vehicles on the horizon. Safety in automotive vehicles is paramount because a failure in execution may result in significant injury or loss of lives. Thus, it is imperative that the application's execution is both functionally correct and guaranteed to be temporally within the bounds established by the application. For example, a delay in braking may have catastrophic consequences. This makes automotive vehicles an example of a safety-critical system. A central tenet in designing automotive vehicles is ensuring that they are certified. For example, ISO-26262 is a standard for automotive safety-critical systems (ASCSs). Certification includes processes that ensure the functionality is correct, and that the temporal behaviour of the application is within pre-determined deadlines. Providing assurances that an execution never exceeds a deadline is extremely challenging. This is because the underlying computing components lack timing predictability. That is, it is difficult to determine how long an application would take to execute in the worst case. This difficulty is attributed to the design of the computing components and their integration to form a system-on-chip (SoC). For example, current SoCs in ASCSs are complex with multiple cores, shared memories, and custom hardware. It is not surprising that they lack timing predictability. Nonetheless, such SoCs are highly coveted as they significantly reduce costs, improve performance, and are energy efficient. The overarching goal of my research program is to design predictable and high performance heterogeneous multicore SoCs for ASCSs. This proposal has five research objectives: (1) investigate predictable cache coherence mechanisms with practical memory hierarchies and scalable directory-based protocols; (2) design predictable and coherent data communication mechanisms across heterogeneous computing elements; (3) develop programming language extensions to annotate properties of data sharing useful for worst-case analyses; (4) develop predictable virtualization for ASCS; and, (5) implement a prototype. The results from this research will have long-lasting impact on both the Canadian economy and society. Industries of varying sizes will be able to evaluate the proposed techniques, and potentially adopt them into their products. The results may spawn innovative industries that, for example, may focus on providing customized solutions such as real-time operating systems specifically designed to support predictable multicore SoCs.