Achieving predictability, repeatability and performance for hard real-time embedded systems

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In order to use chip-multiprocessors (CMP)s for hard real-time embedded computing (HRTEC), we need to innovate computer architectural techniques that exhibit predictable and repeatable timing behaviours, and those that simultaneously enhance performance. This is because HRTEC makes timeliness a criterion for correctness, and ensuring that timing requirements are always met is of critical importance. These timing requirements are ensured through accurate worst-case execution time (WCET) analysis. Unfortunately, modern uniprocessors and CMP architectures are designed with the perspective that faster is always better; thus, employing architectural techniques such as speculative execution, cache-coherency protocols, and best-effort routing. The resulting designs are poorly suited to HRTEC because WCET analysis either requires heroic efforts or is just intractable. In addition, such designs do not scale to CMP architectures.