Parallel simulation of digital hardware models on AMD GPUs

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This research addresses the challenge of accelerating simulation of digital hardware system models by utilizing the parallelism offered by modern multicore CPUs and AMD graphics processing units (GPU)s. In particular, the research will focus on building techniques and a tool that implements these techniques to distribute the simulation of register-transfer level (RTL) models across both the multicore CPUs and the GPUs. Note that SystemC's reference implementation provides a non-parallelizable scheduler. Consequently, the research will first extend SystemCs reference implementation to allow for parallel execution of SystemC models. Then, we will develop a compiler that will analyze SystemC RTL models, and automatically generate OpenCL kernels targeting AMD GPUs. In order to allow for a subset of SystemC processes to execute on the multicore CPUs and others on the GPU, we will develop a wrapper-based technique for cross-communication. We will experimentally evaluate our techniques and tool on benchmarks such as MPEG encoder/decoder, JPEG encoder/decoder, and a Canny edge filter.