Toward a Hardware Architecture for Belief-Desire-Intention-based Agents

随着目前机器人平台和支持它们的操作系统的广泛使用，现在可以使用高级计划监控和执行系统来实现对它们的控制，例如依赖于信念-愿望-意图(BDI)范例的代理框架。BDI允许自主系统的开发人员专注于实现系统可以在其感知(信念)的当前上下文中执行的各种短期计划(意图)和长期目标(愿望)，然后BDI引擎可以在给定当前上下文的情况下选择、执行和监控适当的计划。BDI大多只在模拟或玩具环境中进行评估，因此据我们所知，性能方面，特别是嵌入现实世界时，还没有太多的研究。特别是，BDI周期执行中的实际瓶颈是什么是未知的，那么硬件加速解决这些瓶颈的机会是什么？为了这个目标，我们想研究专门适合BDI系统的硬件体系结构的设计。虽然深度学习在GPU的超级流水线、高度并行的结构上蓬勃发展，但还没有找到BDI的理想架构。我们的假设是，这将需要高度异构性的处理，并与反映BDI实现的数据结构和访问模式的存储器层次互连。我们将建立一个剖析系统，允许我们检测典型的BDI实现，并设计策略来自动派生反映所收集的剖析的硬件架构(通过组合高级综合工具和定制硬件代码生成器)。对于每个架构，我们将评估BDI应用程序集的性能和功耗，并评估瓶颈。

With the current wide availability of robotic platforms and the operating systems to support them, it is now possible to implement their control using high-level plan monitoring and execution systems such as agent frameworks that rely on the Belief-Desire-Intention (BDI) paradigm. BDI allows the developer of an autonomous system to focus on implementing the various short-term plans (Intentions) and long-term goals (Desires) that the system can execute in the current context of its perceptions (Beliefs), and the BDI engine can then select, execute and monitor the appropriate plan given the current context. BDI has mostly only been evaluated in the context of simulated or toy environments, and so the performance aspects, especially when embedded in the real world, has not been investigated much to our knowledge. In particular, it is unknown what the actual bottlenecks in the execution of the BDI cycle are, and so what are the opportunities for hardware acceleration to address those bottlenecksToward this goal, we want to research the design of hardware architectures specifically suited for BDI systems. Whilst deep learning thrives on the super-pipelined, highly parallel fabric of GPUs, an ideal architecture for BDI has not been found. Our hypothesis is that this will require highly heterogeneous processing, interconnected with a memory hierarchy that reflects the data structures and access patterns representative of BDI implementations.We will set up a profiling system that allows us to instrument representative BDI implementations, and design strategies for automatically deriving hardware architectures that reflect the gathered profiles (through a combination of High Level Synthesis tools and custom hardware code generators). For each architecture, we will evaluate performance and power consumption for the set of BDI applications and assess bottlenecks.