A Route to Obtaining Low-Defect III–V Epilayers on Si(100) Utilizing MOCVD
A Route to Obtaining Low-Defect III–V Epilayers on Si(100) Utilizing MOCVD
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利用 MOCVD 在 Si(100) 上获得低缺陷 IIIâV 外延层的途径
DOI：
10.1021/acs.cgd.1c00410
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发表时间：
2021
影响因子：
3.8
通讯作者：
M. Nandy
中科院分区：
文献类型：
--
作者：
M. Nandy
在Si（100）上生长的低缺陷III-V多层结构为广泛的具有成本效益的高性能光伏和光电子器件提供了机会。因此，在Si（100）衬底上制备的几乎与晶格匹配的（Al）GaP涂层可以作为后续异质外延生长的高质量虚拟衬底。在第一步制备过程中，即III-V-on-Si成核过程中，晶体缺陷（如层错金字塔或穿线位错）的演变需要被阻止，因为它们倾向于扩展到随后生长的层中，并增加非辐射电子-空穴复合率，最终降低器件性能。在金属有机化学气相沉积制备的Si（100）衬底上建立了三元GaP/AlP脉冲成核工艺，并将其与纯GaP成核层（NLs）的缺陷演化进行了比较。利用反射各向异性光谱学对整个过程进行了原位光学监测。利用电子通道对比成像技术对晶体缺陷进行了研究。与在二元GaP/AlP NLs上生长的缓冲层相比，在GaP/AlP NLs上生长的缓冲层的螺纹位错和层错密度分别显著降低了1个和2个数量级。我们观察到，与在纯GaP NLs上生长的缓冲层相比，这些缓冲层在生长初期的表面形貌明显光滑。本文提出的成核过程应该可以大大提高集成在Si（100）晶圆上的III-V缓冲层的结晶质量。
Low-defect III–V multilayer structures grown on Si(100) open opportunities for a wide range of cost-effective high-performance photovoltaic and optoelectronic devices. For that, (Al)GaP epilayers prepared almost lattice-matched on Si(100) substrates can serve as high-quality virtual substrates for subsequent heteroepitaxial growth. The evolution of crystal defects, such as stacking fault pyramids or threading dislocations, needs to be impeded already during the first preparation step, the III–V-on-Si nucleation, as they tend to propagate into the subsequently grown layers and increase nonradiative electron–hole recombination rates, which finally degrade the device performance. We establish a ternary GaP/AlP pulsed nucleation process on Si(100) substrates fabricated by metalorganic chemical vapor deposition, and compare it to the defect evolution from pure GaP nucleation layers (NLs). The entire procedure was optically monitored in situ using reflection anisotropy spectroscopy. Crystal defects were investigated by electron channeling contrast imaging. GaP grown on GaP/AlP NLs exhibits drastically reduced densities of threading dislocations and stacking faults by 1 and 2 orders of magnitude, respectively, compared to buffer layers grown on binary GaP NLs. We observed that the surface morphology at the initial stage of growth of these buffer layers is significantly smoother compared to the buffer layers grown on pure GaP NLs using atomic force microscopy. The proposed nucleation procedure here is supposed to substantially improve the crystalline quality of III–V buffer layers integrated on Si(100) wafers.
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