A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology

A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology
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部分 SOI 技术中具有阶梯掺杂漂移区的高压 (> 600 V) N 岛 LDMOS

DOI:
10.1109/ted.2015.2487345
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发表时间:
2016-05
影响因子:
3.1
通讯作者:
Gaofeng Wang
Gaofeng Wang
中科院分区:
工程技术2区
文献类型:
--
作者:
Miaomiao Ma;Mansun Chan;Jin He;Gaofeng Wang

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提出了一种采用部分绝缘体上硅(PSOI)工艺的具有N岛(NIS)和阶梯掺杂漂移区(SDD)的高压横向双扩散MOSFET。在横向上,SDD区和埋氧化层(BOX)上的NiS引入了两个额外的电场峰,改善了表面电场分布和击穿电压(BV)。在垂直方向上,由于NiS的高掺杂,在箱层中感应出更高的电场,从而可以获得更高的垂直BV。因此,BV得到了显著增强。此外,掺杂浓度越大的NIS可以提供更高的电流,从而降低了导通电阻(RON)。二维模拟结果表明,该结构的BV可达680V,与传统PSOI和n型埋层PSOI相比,RON分别降低了10.2%和14.7%。
A high-voltage lateral double-diffused MOSFET with N-island (NIS) and step-doped drift (SDD) region in partial silicon-on-insulator (PSOI) technology is proposed. In the lateral direction, the SDD region and the NIS on the buried oxide layer (BOX) introduce two additional electric field peaks, which can improve the surface field distribution and breakdown voltage (BV). In the vertical direction, due to the highly doped NIS, a higher electric field is induced into the BOX layer, which can achieve a higher vertical BV. As a consequence, the BV is enhanced significantly. Moreover, the NIS with a larger doping concentration can provide a higher current of the proposed device, and thus, the ON-resistance (RON) is reduced. The 2-D simulation results show that the BV of the proposed structure can achieve 680 V, and RON is reduced by 10.2% and 14.7% in comparison with the conventional PSOI and buried n-type layer PSOI, respectively.
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