Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications

Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
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针对器件应用的独立式 3C-SiC 层 MOS 接口的初步研究

DOI:
10.1088/1361-6641/abefa1
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发表时间:
2021
影响因子:
1.9
通讯作者:
Renz A
Renz A
中科院分区:
工程技术4区
文献类型:
--
作者:
Renz A

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本文报告了对同质外延3C-SiC生长工艺的材料质量和器件适宜性的初步研究结果。原子力显微镜表面分析表明,表面均方根粗糙度为163.21 nm,这是由材料生长过程中形成的密度为1.0 9×10 5 cm的凹坑(35μm宽,4 5 0 nm深)造成的。在更宽的扫描区域上,这些缺陷的形成被认为是由阶跃聚束引起的,这表明需要进一步改进外延工艺。X-射线衍射仪显示出良好的平均结晶质量,3C-SiC(002)的半高宽为160角秒,低于3C-on-Si材料的210角秒。C-V曲线分析表明,自支撑的3C-碳化硅、硅上的3C-碳化硅和4H-碳化硅的界面陷阱电荷能级相似,而形成气体后沉积的独立的3C-碳化硅器件的DIT能级为3.3×1011 cm−2 eV−1,E-C-−E-T=0.2 eV。漏电流测量也证实了同质外延生长的3C-SiC材料适用于MOS应用。
This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm width and 450 nm depth) with a density of 1.09× 10 5 cm− 2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C–V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing D IT levels of 3.3× 10 11 cm− 2 eV− 1 at E C− E T= 0.2 eV. The homo-epitaxially grown 3C-SiC material's suitability for MOS applications could also be confirmed by leakage current measurements.
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