Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters.
Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters.
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DOI：
10.1038/nmat3518
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发表时间：
2013-03
期刊：
影响因子：
41.2
通讯作者：
Duan X
中科院分区：
文献类型：
--
作者：
Yu WJ;Li Z;Zhou H;Chen Y;Wang Y;Huang Y;Duan X
像石墨烯这样的层状材料在未来的电子学领域引起了相当大的兴趣。本文报道了层状材料多异质结构的垂直集成，以实现高电流密度垂直场效应晶体管（vfet）。n沟道VFET是通过将几层二硫化钼（MoS2）作为半导体通道夹在单层石墨烯和金属薄膜之间制成的。该vfet具有室温通断比bbb103，同时提供高达5,000 a /cm2的高电流密度，足以满足高性能逻辑应用。本研究提供了垂直整合各种层状材料的一般策略，以获得p沟道和n沟道晶体管，以实现互补的逻辑功能。通过将石墨烯、Bi2Sr2Co2O8 （p沟道）、石墨烯、MoS2 （n沟道）和金属薄膜依次垂直堆叠，展示了具有大于单位电压增益的互补逆变器。在垂直堆叠的多异质结构中同时实现高通断比、高电流密度和逻辑集成的能力，可以为未来电子器件开辟一个新的维度，实现三维集成。
The layered materials such as graphene have attracted considerable interest for future electronics. Here we report the vertical integration of multi-heterostructures of layered materials to enable high current density vertical field-effect transistors (VFETs). An n-channel VFET is created by sandwiching few-layer molybdenum disulfide (MoS2) as the semiconducting channel between a monolayer graphene and a metal thin film. The VFETs exhibit a room temperature on-off ratio >103, while at same time deliver a high current density up to 5,000 A/cm2, sufficient for high performance logic applications. This study offers a general strategy for the vertical integration of various layered materials to obtain both p- and n-channel transistors for complementary logic functions. A complementary inverter with larger than unit voltage gain is demonstrated by vertically stacking the layered materials of graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel), and metal thin film in sequence. The ability to simultaneously achieve high on-off ratio, high current density, and logic integration in the vertically stacked multi-heterostructures can open up a new dimension for future electronics to enable three-dimensional integration.
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