A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology
A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology
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采用累积模式扩展栅极和背面刻蚀技术的均匀掺杂超薄SOI LDMOS
DOI：
10.1088/1674-1056/25/2/027306
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发表时间：
2016-02
影响因子：
1.7
通讯作者：
Luo Xiao-Rong
中科院分区：
文献类型：
--
作者：
Zhang Yan-Hui;Wei Jie;Yin Chao;Tan Qiao;Liu Jian-Ping;Li Peng-Cheng;Luo Xiao-Rong
提出了一种具有低比导通电阻（Ron,sp）和高击穿电压（BV）的均匀掺杂超薄绝缘体上硅（SOI）横向双扩散金属氧化物半导体（LDMOS），并对其机理进行了研究。所提出的LDMOS具有累积模式扩展栅极（AG）和背面蚀刻（BE）的特点。扩展栅极由一个P区和两个串联二极管组成。在VGD为>的导通状态下，AG下沿漂移区表面形成电子积累层。它提供了沿整个漂移区表面的超低阻电流路径，从而使该新型器件获得了低温分布。Ron，sp几乎与漂移区掺杂浓度无关。在关断状态下，AG不仅调节了表面电场分布，提高了BV，还带来了电荷补偿效应，进一步降低了Ron，sp。此外，BE避免了垂直过早击穿以获得高BV，并允许在漂移区均匀掺杂，从而避免了可变横向掺杂（VLD）和由VLD引起的“热点”。与VLD SOI LDMOS相比，该器件同时降低了70.2%的Ron，sp，并将BV从776 V提高到818 V。
A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the "hot-spot" caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V.
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影响因子：
3.1
作者：
Yu Chen;Y.C. Liang;G. Samudra;Xin Yang;K. Buddharaju;Hanhua Feng
通讯作者：
Yu Chen;Y.C. Liang;G. Samudra;Xin Yang;K. Buddharaju;Hanhua Feng
影响因子：
3.1
作者：
Xinjiang Lyu;Xingbi Chen
通讯作者：
Xinjiang Lyu;Xingbi Chen
DOI：
10.1109/ispsd.2008.4538965
发表时间：
2008-05
期刊：
2008 20th International Symposium on Power Semiconductor Devices and IC's
影响因子：
--
作者：
T. Trajkovic;F. Udrea;C. Lee;N. Udugampola;V. Pafhirana;A. Mihaila;G. Amaratunga
通讯作者：
T. Trajkovic;F. Udrea;C. Lee;N. Udugampola;V. Pafhirana;A. Mihaila;G. Amaratunga
DOI：
10.1109/pesc.2001.954439
发表时间：
2001-06
期刊：
2001 IEEE 32nd Annual Power Electronics Specialists Conference (IEEE Cat. No.01CH37230)
影响因子：
--
作者：
K. Gan;Y.C. Liang;G. Samudra;S. Xu;L. Yong
通讯作者：
K. Gan;Y.C. Liang;G. Samudra;S. Xu;L. Yong
具有增强击穿电压的新型低导通电阻 LDMOS
影响因子：
3.1
作者：
Xiaorong Luo;Jie Wei;Xianlong Shi;Kun Zhou;Ruichao Tian;Zhang Bo;Li Zhaoji
通讯作者：
Li Zhaoji