Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
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了解和减轻 NMOS HKMG 器件引起的布局依赖性的应力记忆技术
DOI:
10.1109/jeds.2020.3032957
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发表时间:
2021
影响因子:
2.3
通讯作者:
Tian Chun Ye
中科院分区:
文献类型:
--
作者:
Ying-Fei Wang;Qing-Chun Zhang;Ping Li;Xiaojing Su;Lisong Dong;Rui Chen;Libin Zhang;Tianyang Gai;Yajuan Su;Wei Yayi;Tian Chun Ye
For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and length of diffusion effect. Based on the oxygen diffusion mechanism analysis of layout proximity effects in high-k/Metal gate NMOS device, an optimized process is proposed to suppress the layout dependency. The experiment result indicates that modified low temperature stress memorization technique process can suppress layout dependency efficiently without performance degradation of the devices.
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期刊:
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期刊:
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期刊:
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