Understanding Vmin Failures for Improved Testing of Timing Marginalities
Understanding Vmin Failures for Improved Testing of Timing Marginalities
复制标题
了解 Vmin 故障以改进时序裕度测试
DOI：
10.1109/itc50671.2022.00046
复制
发表时间：
2022
期刊：
影响因子：
--
通讯作者：
Singh, Adit D.
中科院分区：
文献类型：
--
作者：
Singh, Adit D.
有人猜测，在操作中越来越多地观察到的许多不可预测和难以诊断的间歇性错误的来源是在低电压操作中加重的定时边缘性，其在测试期间逃避检测。为了研究这种可能性，我们提出了一个全面的研究，结合分析建模与仿真，随机工艺变化的CMOS门和电路路径的时序的影响时，在显着降低电压。我们的分析得到了一个大型工业团队最近发布的先进FinFET技术生产测试数据的验证[1]。这项研究中一个关键的、有点出乎意料的观察结果是，几乎所有的变异路径都是统计异常值，慢到足以导致定时故障，都包含一个极弱的晶体管，它在增加的延迟中占很大比例。这表明，TDF定时测试，目标定位的“集总”延迟缺陷，也可以检测到许多定时故障所造成的分布延迟过程的变化。至少部分地减轻了感知到的针对此类故障的路径延迟测试的需要。我们进一步展示了如何在本文中的分析结果可以利用调理的电压和定时的应用TDF扫描测试，以帮助提高检测的边缘定时部分，从而减少测试逃逸和最大限度地减少系统级测试。
There has been speculation that the source of many of the unpredictable and hard to diagnose intermittent errors being increasingly observed in operation are timing marginalities, accentuated in low voltage operation, that escape detection during test. To investigate this possibility, we present a comprehensive study, combining analytical modeling with simulation, of the impact of random process variations on the timing of CMOS gates and circuit paths when operating at significantly reduced voltages. Our analysis is validated with the help of production test data recently published by a large industrial team for an advanced FinFET technology [1]. A key, somewhat unexpected, observation from this study is that virtually all variability paths that are statistical outliers, slow enough to cause timing failure, contain a single extremely weak transistor which contributes a large share of the increased delay. This suggests that TDF timing tests, that target localized “lumped” delay defects, may also detect many timing failures caused by distributed delays from process variations. The perceived need for path delay testing to target such failures is at least partially mitigated. We further show how the results of the analysis in this paper can be leveraged for conditioning the voltage and timing of the applied TDF scan tests to help enhance detection of such marginal timing parts, thereby reducing test escapes and minimizing system level tests.
登录
查看更多内容
探索系统级测试的奥秘
DOI：
10.1109/ats49688.2020.9301557
发表时间：
2020
期刊：
2020 IEEE Asian Test Symposium
影响因子：
--
作者：
Polian, Ilia;Anders, Jens;Becker, Steffen;Bernardi, Paolo;Chakrabarty, Krishnendu;ElHamawy, Nourhan;Sauer, Matthias;Singh, Adit;Reorda, Matteo Sonza;Wagner, Stefan
通讯作者：
Wagner, Stefan
最大限度地减少针对低电压 DVFS 故障的系统级测试的自适应方法
DOI：
10.1109/itc44170.2019.9000173
发表时间：
2019
期刊：
2019 IEEE International Test Conference (ITC
影响因子：
--
作者：
Singh, Adit D.
通讯作者：
Singh, Adit D.
7nm FinFet 中的 Shockley 和 Sakurai 行为模型
DOI：
10.1109/iemtronics51293.2020.9216418
发表时间：
2020
期刊：
2020 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS)
影响因子：
--
作者：
M. Anees;K. Rahul;Sourabh Aditya Swarnkar;Santosh Yachareni
通讯作者：
Santosh Yachareni
32 纳米笔记本处理器的细胞感知生产测试结果
DOI：
10.1109/test.2012.6401533
发表时间：
2012
期刊：
2012 IEEE International Test Conference
影响因子：
--
作者：
F. Hapke;Michael Reese;J. Rivers;A. Over;V. Ravikumar;W. Redemund;Andreas Glowatz;J. Schlöffel;J. Rajski
通讯作者：
J. Rajski
交流扫描测试期间校准时钟延伸
DOI：
--
发表时间：
2005
期刊：
IEEE International Conference on Test, 2005.
影响因子：
--
作者：
J. Rearick;R. Rodgers
通讯作者：
R. Rodgers