Simulation of electrical characteristics and structural optimization for small-scaled dual-gate GeOI MOSFET with high-k gate dielectric
Simulation of electrical characteristics and structural optimization for small-scaled dual-gate GeOI MOSFET with high-k gate dielectric
复制标题
高k栅介质小尺寸双栅GeOI MOSFET电特性仿真及结构优化
DOI：
10.1088/1674-4926/35/9/094002
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发表时间：
2014-09
影响因子：
5.1
通讯作者：
M.M. Fan
中科院分区：
文献类型：
--
作者：
Y.R. Bai;J.P. Xu;L. Liu;M.M. Fan
利用二维器件模拟器研究了双栅GeOI MOSFET的主要结构和物理参数对器件性能的影响。通过分析GeOI MOSFET的导通电流、关断电流、短通道效应（SCE）和漏极降垒效应（DIBL），确定了锗（Ge）沟道厚度、掺杂浓度、栅极氧化物厚度和介电常数的合理取值范围。当沟道厚度和掺杂浓度分别为10 ~ 18 nm和（5 ~ 9）× 1017 cm−3，栅极介电介质等效氧化物厚度为0.8 ~ 1 nm和介电常数分别为15 ~ 30时，可获得良好的器件性能：导通电流大于1475 μA/μm，关断电流小于0.1 μA/μm， sce诱导阈值电压漂移小于60 mV， dibl诱导阈值电压漂移小于140 mV。
The influences of the main structure and physical parameters of the dual-gate GeOI MOSFET on the device performance are investigated by using a TCAD 2D device simulator. A reasonable value range of germanium (Ge) channel thickness, doping concentration, gate oxide thickness and permittivity is determined by analyzing the on-state current, off-state current, short channel effect (SCE) and drain-induced barrier lowering (DIBL) effect of the GeOI MOSFET. When the channel thickness and its doping concentration are 10–18 nm and (5–9) × 1017 cm−3, and the equivalent oxide thickness and permittivity of the gate dielectric are 0.8–1 nm and 15–30, respectively, excellent device performances of the small-scaled GeOI MOSFET can be achieved: on-state current of larger than 1475 μA/μm, off-state current of smaller than 0.1 μA/μm, SCE-induced threshold-voltage drift of lower than 60 mV and DIBL-induced threshold-voltage drift of lower than 140 mV.
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影响因子：
1.5
作者：
Y. Tahara;Y. Omura
通讯作者：
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影响因子：
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作者：
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通讯作者：
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影响因子：
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作者：
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