Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
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具有嵌入式时钟门控方案的高能效双边沿隐式脉冲触发触发器
DOI:
10.1631/fitee.1500293
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发表时间:
2016-10
影响因子:
3
通讯作者:
Xu Cong-yuan
中科院分区:
文献类型:
--
作者:
Geng Liang;Shen Ji-zhong;Xu Cong-yuan
A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.
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DOI:
10.1109/tvlsi.2009.2029116
发表时间:
2011
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