Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
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具有嵌入式时钟门控方案的高能效双边沿隐式脉冲触发触发器

DOI:
10.1631/fitee.1500293
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发表时间:
2016-10
影响因子:
3
通讯作者:
Xu Cong-yuan
Xu Cong-yuan
中科院分区:
工程技术3区
文献类型:
--
作者:
Geng Liang;Shen Ji-zhong;Xu Cong-yuan

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提出了一种新颖的具有嵌入式时钟门控方案的双边沿隐式脉冲触发触发器(DIFF-CGS),该触发器在脉冲生成阶段采用基于传输门逻辑(TGL)的时钟门控方案。该方案在输入数据保持不变时有条件地禁用反相器链,因此延迟时钟信号和锁存器内部节点的冗余转换全部被消除,导致低功率效率。基于中芯国际 65 nm 技术,广泛的布局后仿真结果表明,与数据交换活动为 10% 的同类产品相比,所提出的 DIFF-CGS 在功耗方面提高了 41.39% 至 56.21%。此外,隐式脉冲生成和静态锁存器中的全摆幅操作提高了设计的稳健性。因此,DIFF-CGS 适用于数据交换活动较少的超大规模集成 (VLSI) 设计中的低功耗应用。
A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.
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