Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies
Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies
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65 nm 双井和三井 CMOS 技术中虚拟栅极隔离逻辑节点间单粒子瞬态脉冲猝灭的表征
DOI：
10.1109/tns.2015.2469740
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发表时间：
2015-09
影响因子：
1.8
通讯作者：
Liang Bin
中科院分区：
文献类型：
--
作者：
Chen Jianjun;Chen Shuming;Chi Yaqing;Liang Bin
随着芯片技术尺寸的缩小，单个高能离子撞击通常会影响多个相邻的逻辑节点。由单粒子电荷共享收集引起的所谓的脉冲猝灭效应已经被广泛地探索，以努力找到用于单粒子瞬变（SET）或单粒子翻转（SEU）的缓解技术，并且伪栅极隔离已经被证明是用于脉冲猝灭增强的有效布局技术。在本文中，在65 nm双阱和三阱CMOS工艺中，虚栅隔离逻辑节点之间的SET脉冲猝灭的表征。利用四组重离子实验对脉冲猝灭效应进行了研究，并对脉冲猝灭效应进行了定量分析。在双阱和三阱CMOS工艺中，脉冲猝灭效应表现出不同的特性。
As chip technologies scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes. The so-called pulse quenching effect, induced by single-event charge sharing collection, has been widely explored in efforts to find mitigation techniques for single-event transients (SETs) or single-event upsets (SEUs), and the dummy gate isolation has been proven to be an efficient layout technique for pulse quenching enhancement. In this paper, the characterization of SET pulse quenching among dummy gate isolated logic nodes is performed in 65 nm twin-well and triple-well CMOS technologies. Four groups of heavy ion experiments are explored for the characterization, and the pulse quenching effect is quantitatively analyzed in detail. The pulse quenching effects show different characteristics in twin-well and triple-well CMOS technologies.
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DOI：
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发表时间：
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影响因子：
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