Research on Topological Design Tools for Structured Logic Arrays

结构化逻辑阵列拓扑设计工具研究

• 批准号: 8419744
• 负责人: Gary Hachtel
• 金额: $ 39.45万
• 依托单位: University of Colorado at Boulder
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1985
• 资助国家: 美国
• 起止时间: 1985-09-15 至 1988-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8419744&HistoricalAwards=false
• 关键词: Research; Topological; Design; Tools; Structured

Research continues on highly automated software tools which produce VLSI-structured logic designs which are correct by construction. Emphasis in the research is on synthesis of multilevel Boolean Networks with the following specific research objectives: satisfy all ;ita priori;ro design rules, specifications, and constraints whenever possible; and provide a unified theory of disparate logic synthesis techniques, including 2-level logic minimization methods, local transformation, don't-care techniques, and others. A longer-range objective is an investigation of possible applications of these synthesis techniques at the functional level. The final goal is "silicon compilation," i.e., automated synthesis of a given behavioral specification (e.g., system architecture and instruction set) into specified target layout technologies. Test cases of complete microprocessor synthesis are studied.

对高度自动化软件工具的研究仍在继续，这些工具可生成通过构造正确的 VLSI 结构化逻辑设计。 研究的重点是多级布尔网络的综合，具有以下具体研究目标：尽可能满足所有先验的设计规则、规范和约束；并提供不同逻辑综合技术的统一理论，包括2级逻辑最小化方法、局部变换、无关技术等。 更长远的目标是研究这些合成技术在功能水平上的可能应用。 最终目标是“硅编译”，即将给定的行为规范（例如系统架构和指令集）自动合成指定的目标布局技术。 研究了完整微处理器综合的测试用例。