An Integrated VHDL-based Synthesis and Verification System for VLSI Systems

用于 VLSI 系统的基于 VHDL 的集成综合和验证系统

• 批准号: 9422268
• 负责人: Gary Hachtel
• 金额: $ 77.32万
• 依托单位: University of Colorado at Boulder
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1995
• 资助国家: 美国
• 起止时间: 1995-06-15 至 1999-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9422268&HistoricalAwards=false
• 关键词: Integrated; VHDL; based; Synthesis; Verification

This research is on synthesis and verification of digital systems. The computational basis for the work is the binary decision diagram (BDD) data structure and extensions. In low power circuit design, new ideas in BDD technology are being used for synthesis algorithms, and to estimate power consumption via probablistic behavior of circuits. Decomposition concepts, such as tearing, to assess properties of very large circuits are being investigated. In verification, approximate exploration ideas are being examined for use in checking equivalence of very large circuits. Hierarchical verification capabilities, where parts of the circuit are modeled at the bit level and other parts at the word level, are being examined. To provide a sound connection between high level synthesis and high level verification, as well as to validate high level VHDL descriptions, refined comparisons of non-deterministic systems, such as bi-simulation equivalence and testing equivalence and pre-orders are being explored.

本课题研究的是数字系统的综合与验证。这项工作的计算基础是二叉决策图(BDD)数据结构和扩展。在低功耗电路设计中，BDD技术的新思想被用于综合算法，并通过电路的概率行为来估计功耗。人们正在研究分解概念，如撕裂，以评估超大型电路的性能。在验证中，正在研究用于检查超大型电路的等价性的近似探索思想。正在审查分层验证能力，其中电路的部分在位级建模，而其他部分在字级建模。为了在高级综合和高级验证之间提供良好的连接，以及验证高级VHDL语言描述，正在探索非确定性系统的精细比较，例如双模拟等价性和测试等价性和预排序。