An Integrated VHDL-based Synthesis and Verification System for VLSI Systems

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This research is on synthesis and verification of digital systems. The computational basis for the work is the binary decision diagram (BDD) data structure and extensions. In low power circuit design, new ideas in BDD technology are being used for synthesis algorithms, and to estimate power consumption via probablistic behavior of circuits. Decomposition concepts, such as tearing, to assess properties of very large circuits are being investigated. In verification, approximate exploration ideas are being examined for use in checking equivalence of very large circuits. Hierarchical verification capabilities, where parts of the circuit are modeled at the bit level and other parts at the word level, are being examined. To provide a sound connection between high level synthesis and high level verification, as well as to validate high level VHDL descriptions, refined comparisons of non-deterministic systems, such as bi-simulation equivalence and testing equivalence and pre-orders are being explored.