Research Initiation: Study of a New Built-in Self-Test Architecture

正在研究一种新的内置自检架构，可以更好地利用并行处理。在传统的内建自测试算法中，伪随机模式生成器和签名寄存器不并行操作。本研究的目的是研究一种新的内建自测试架构，该架构在为一个模块生成测试模式的同时，收集其他测试模块的测试模式的响应。由此产生的设计将是面积效率高，具有并行测试，并具有简单的控制电路。随着VLSI技术的快速发展和VLSI电路复杂性的增加，由于对内部模式的访问能力较差，传统的测试方法将测试模式存储在测试设备中并应用于芯片的外部引脚，因此可能不具有成本效益。通过内置的自检方案，测试模式和测试响应评估器被放置在同一芯片中。提高内建自测试并行性的研究在复杂VLSI电路中具有十分重要的意义。首席研究员是一名新博士，他的研究已经取得了重大进展。研究集中在重要而及时的主题上。强烈建议您提供支持。

A new built-in self-test architecture that can better exploit parallel processing is being studied. In conventional built-in self-test algorithms, the pseudorandom pattern generators and signature registers do not operate in parallel. The goal of this research is to study a new built-in self-test architecture that generates the test pattern for one module while collecting responses of test patterns of other test modules. The resulting design will be area efficient, have parallel testing, and have simple control circuity. With the rapid growth of VLSI technology and increased complexity of VLSI circuits, conventional test methods in which the test patterns are stored in test equipment and are applied to the external pins of the chip may not be cost effective due to the poor accessibility to internal modes. With a built-in self-test scheme, test patterns and test response evaluators are placed in the same chip. The research of enhancing parallelism in built-in self-test is very important in complex VLSI circuits. The principal investigator is a new Ph.D. who already has significant progress in his research. The research focuses on important and timely topics. Support is highly recommended.