Research Initiation: Study of a New Built-in Self-Test Architecture

一种新的内置自测试架构，可以更好地利用并行 加工正在研究中。 在传统的内置自测试中， 算法、伪随机模式发生器和签名寄存器 不要并行操作。 本研究的目的是研究一种 新的内置自测试架构，可生成测试模式， 一个模块同时收集其它测试的测试模式的响应 模块。 由此产生的设计将是面积有效的，具有平行 测试，控制电路简单。 随着超大规模集成电路（VLSI）技术的快速发展和 VLSI电路，常规测试方法，其中测试图案是 存储在测试设备中，并施加到 芯片可能是不符合成本效益，由于穷人的可达性， 内部模式 通过内置的自测试方案，测试模式和 测试响应评估器被放置在同一芯片中。 的研究 增强内建自测试中的并行性非常重要， 复杂的超大规模集成电路 首席研究员是一位新博士。他已经有了很大的 他的研究进展。 研究重点是重要和及时的 话题 强烈建议提供支持。

A new built-in self-test architecture that can better exploit parallel processing is being studied. In conventional built-in self-test algorithms, the pseudorandom pattern generators and signature registers do not operate in parallel. The goal of this research is to study a new built-in self-test architecture that generates the test pattern for one module while collecting responses of test patterns of other test modules. The resulting design will be area efficient, have parallel testing, and have simple control circuity. With the rapid growth of VLSI technology and increased complexity of VLSI circuits, conventional test methods in which the test patterns are stored in test equipment and are applied to the external pins of the chip may not be cost effective due to the poor accessibility to internal modes. With a built-in self-test scheme, test patterns and test response evaluators are placed in the same chip. The research of enhancing parallelism in built-in self-test is very important in complex VLSI circuits. The principal investigator is a new Ph.D. who already has significant progress in his research. The research focuses on important and timely topics. Support is highly recommended.