Research Initiation: Study of a New Built-in Self-Test Architecture

一种能够更好地利用并行处理的内置自检架构正在研究中。在传统的内置自检算法中，伪随机模式生成器和签名寄存器不能并行运行。本研究的目标是研究一种新的内置自测体系结构，该体系结构生成一个模块的测试模式，同时收集其他测试模块的测试模式响应。所得到的设计将是面积有效，可并行测试，并具有简单的控制电路。随着VLSI技术的快速发展和VLSI电路复杂性的增加，传统的测试方法将测试模式存储在测试设备中并应用于芯片的外部引脚，由于内部模式难以获得，可能不具有成本效益。使用内置的自测方案，测试模式和测试响应评估器被放置在同一芯片中。在复杂的VLSI电路中，提高内置自检并行性的研究是非常重要的。首席研究员是一位新博士，他的研究已经取得了重大进展。研究集中在重要和及时的主题。强烈建议提供支持。

A new built-in self-test architecture that can better exploit parallel processing is being studied. In conventional built-in self-test algorithms, the pseudorandom pattern generators and signature registers do not operate in parallel. The goal of this research is to study a new built-in self-test architecture that generates the test pattern for one module while collecting responses of test patterns of other test modules. The resulting design will be area efficient, have parallel testing, and have simple control circuity. With the rapid growth of VLSI technology and increased complexity of VLSI circuits, conventional test methods in which the test patterns are stored in test equipment and are applied to the external pins of the chip may not be cost effective due to the poor accessibility to internal modes. With a built-in self-test scheme, test patterns and test response evaluators are placed in the same chip. The research of enhancing parallelism in built-in self-test is very important in complex VLSI circuits. The principal investigator is a new Ph.D. who already has significant progress in his research. The research focuses on important and timely topics. Support is highly recommended.