Infrastructure for VLSI Circuit Testing: Development of a Fault Simulator and Test Generators for Industrial Circuits

VLSI 电路测试基础设施：工业电路故障模拟器和测试发生器的开发

• 批准号: 9632625
• 负责人: Dong Ha
• 金额: $ 17.47万
• 依托单位: Virginia Polytechnic Institute and State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1996
• 资助国家: 美国
• 起止时间: 1996-09-01 至 1999-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9632625&HistoricalAwards=false
• 关键词: Infrastructure; VLSI; Circuit; Testing; Development

VLSI chip testing tools, produced in research projects at the Virginia Polytechnic University, are being developed and enhanced. The tools are intended to support teaching and research in academia. These tools include, a combinational circuit automatic test pattern generator (ATPG), a sequential fault simulator, a sequential ATPG for both synchronous and asynchronous sequential circuits, and two parsers for analyzing circuit designs in the languages VHDL and EDIF. A benchmark collection of industrial type circuits is being developed. The tools are being developed so that they: 1. are easy to install and use, and are maintenance free; 2. provide a variety of options to support many research and teaching activities; and 3. the source code is easy to read, modify and extend. The tools and their source code are being distributed freely to universities for research and teaching.

在弗吉尼亚理工大学的研究项目中生产的超大规模集成电路芯片测试工具正在开发和改进中。 这些工具旨在支持学术界的教学和研究。 这些工具包括，一个组合电路自动测试模式生成器（ATPG），一个顺序故障模拟器，一个顺序ATPG同步和异步时序电路，和两个分析器用于分析电路设计的语言VHDL和EDIF。 正在开发工业类型电路的基准集合。 正在开发的工具，以便他们：1。易于安装和使用，并且免维护; 2.提供多种选择，以支持许多研究和教学活动;以及3.源代码易于阅读，修改和扩展。 这些工具及其源代码正在免费分发给各大学用于研究和教学。