Infrastructure for VLSI Circuit Testing: Development of a Fault Simulator and Test Generators for Industrial Circuits

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VLSI chip testing tools, produced in research projects at the Virginia Polytechnic University, are being developed and enhanced. The tools are intended to support teaching and research in academia. These tools include, a combinational circuit automatic test pattern generator (ATPG), a sequential fault simulator, a sequential ATPG for both synchronous and asynchronous sequential circuits, and two parsers for analyzing circuit designs in the languages VHDL and EDIF. A benchmark collection of industrial type circuits is being developed. The tools are being developed so that they: 1. are easy to install and use, and are maintenance free; 2. provide a variety of options to support many research and teaching activities; and 3. the source code is easy to read, modify and extend. The tools and their source code are being distributed freely to universities for research and teaching.