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Software Capitalization: CAD Tools for VLSI Circuit Testing

Software Capitalization: CAD Tools for VLSI Circuit Testing
软件资本化：用于 VLSI 电路测试的 CAD 工具
批准号：
9310115
负责人：
Dong Ha
金额：
$3.86万
依托单位：
Virginia Polytechnic Institute and State University
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
1993
资助国家：
美国
项目状态：
已结题
起止时间：
1993-07-01 至 1994-12-31
来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=9310115&HistoricalAwards=false
关键词：
SoftwareCapitalizationCADToolsVLSI

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中文摘要
翻译
Ha 目前正在开发和改进弗吉尼亚理工学院研究项目中生产的四个故障模拟器和自动测试模式发生器，以便将其推广到一般用户。 这些工具是：1. 组合电路故障模拟器; 2. HOPE，同步顺序故障模拟器; 3. ATALANTA，一种用于组合电路中固定故障的ATPG;以及4. SOPRANO是一种用于组合电路中开路故障的ATPG。
英文摘要
Ha Four fault simulators and automatic test pattern generators (ATPGs), produced in research projects at the Virginia Polytechnic Institute, are being developed and enhanced so as to bring them into a state for distribution to general users. These tools are: 1. FSIM, combinational circuit fault simulator; 2. HOPE, a synchronous sequential fault simulator; 3. ATALANTA, an ATPG for stuck-at faults in combinational circuits; and 4. SOPRANO, an ATPG for stuck-open faults in combinational circuits.
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