Software Capitalization: CAD Tools for VLSI Circuit Testing

软件资本化：用于 VLSI 电路测试的 CAD 工具

• 批准号: 9310115
• 负责人: Dong Ha
• 金额: $ 3.86万
• 依托单位: Virginia Polytechnic Institute and State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1993
• 资助国家: 美国
• 起止时间: 1993-07-01 至 1994-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9310115&HistoricalAwards=false
• 关键词: Software; Capitalization; CAD; Tools; VLSI

Ha Four fault simulators and automatic test pattern generators (ATPGs), produced in research projects at the Virginia Polytechnic Institute, are being developed and enhanced so as to bring them into a state for distribution to general users. These tools are: 1. FSIM, combinational circuit fault simulator; 2. HOPE, a synchronous sequential fault simulator; 3. ATALANTA, an ATPG for stuck-at faults in combinational circuits; and 4. SOPRANO, an ATPG for stuck-open faults in combinational circuits.

在弗吉尼亚理工学院的研究项目中生产的四个故障模拟器和自动测试图形生成器(ATPG)正在开发和改进，以使其进入分发给一般用户的状态。这些工具是：1.组合电路故障模拟器FSIM；2.同步顺序故障模拟器HOPE；3.ATALTA，组合电路中固定故障的ATPG；4.Soprano，组合电路中固定故障的ATPG。